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74ACT16245SSC [FAIRCHILD]

16-Bit Transceiver with 3-STATE Outputs; 16位收发器与3态输出
74ACT16245SSC
型号： 74ACT16245SSC
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

16-Bit Transceiver with 3-STATE Outputs
16位收发器与3态输出

逻辑集成电路 光电二极管
文件： 总6页 (文件大小：82K)
中文：  中文翻译
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August 1999  
Revised May 2005  
74ACT16245  
16-Bit Transceiver with 3-STATE Outputs  
General Description  
Features  
The ACT16245 contains sixteen non-inverting bidirectional  
buffers with 3-STATE outputs and is intended for bus ori-  
ented applications. The device is byte controlled. Each has  
separate control inputs which can be shorted together for  
full 16-bit operation. The T/R inputs determine the direction  
of data flow through the device. The OE inputs disable both  
the A and B ports by placing them in a high impedance  
state.  
■ Bidirectional non-inverting buffers  
■ Separate control logic for each byte  
■ 16-bit version of the ACT245  
■ Outputs source/sink 24 mA  
■ TTL-compatible inputs  
Ordering Code:  
Order Number  
74ACT16245SSC  
74ACT16245MTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Description  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
Transmit/Receive Input  
Side A Inputs/Outputs  
T/R  
A0–A15  
B0–B15  
Side B Outputs/Inputs  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS500296  
www.fairchildsemi.com  
Functional Description  
The ACT16245 contains sixteen non-inverting bidirectional  
buffers with 3-STATE outputs. The device is byte controlled  
with each byte functioning identically, but independent of  
the other. The control pins can be shorted together to  
obtain full 16-bit operation. The following description  
applies to each byte. When the T/R input is HIGH, then Bus  
A data is transmitted to Bus B. When the T/R input is LOW,  
Bus B data is transmitted to Bus A. The 3-STATE outputs  
are controlled by an Output Enable (OEn) input for each  
byte. When OEn is LOW, the outputs are in 2-state mode.  
When OEn is HIGH, the outputs are in the high impedance  
mode, but this does not interfere with entering new data  
into the inputs.  
Truth Tables  
Inputs  
Outputs  
OE1  
T/R1  
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7  
Bus A0–A7 Data to Bus B0–B7  
HIGH-Z State on A0–A7, B0–B7  
H
Inputs  
Outputs  
OE2  
T/R2  
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15  
Bus A8–A15 Data to Bus B8–B15  
HIGH-Z State on A8–A15, B8–B15  
H
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
High Impedance  
Logic Diagram  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 1)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
DC Input Diode Current (IIK  
VI 0.5V  
VI VCC 0.5V  
DC Output Diode Current (IOK  
VO 0.5V  
)
0.5V to 7.0V  
)
Supply Voltage (VCC  
)
4.5V to 5.5V  
0V to VCC  
20 mA  
20 mA  
Input Voltage (VI)  
Output Voltage (VO)  
0V to VCC  
)
Operating Temperature (TA)  
40 C to 85 C  
125 mV/ns  
20 mA  
20 mA  
Minimum Input Edge Rate ( V/ t)  
VO VCC 0.5V  
V
IN from 0.8V to 2.0V  
DC Output Voltage (VO)  
0.5V to VCC 0.5V  
50 mA  
VCC @ 4.5V, 5.5V  
DC Output Source/Sink Current (IO)  
DC VCC or Ground Current  
per Output Pin  
Note 1: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, with-  
out exception to ensure that the system design is reliable over its power  
supply, temperature, and output/input loading variables. Fairchild does not  
recommend operation of FACT circuits outside databook specifications.  
50 mA  
Storage Temperature  
65 C to 150 C  
DC Electrical Characteristics  
V
T
25 C  
T
A
40 C to 85 C  
CC  
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
V
V
V
Minimum HIGH  
2.0  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
V
0.1V  
IH  
OUT  
V
V
V
Input Voltage  
Maximum LOW  
Input Voltage  
Minimum HIGH  
Output Voltage  
1.5  
2.0  
0.8  
0.8  
4.4  
5.4  
or V  
0.1V  
0.1V  
0.1V  
CC  
1.5  
V
IL  
OUT  
1.5  
or V  
CC  
4.49  
5.49  
OH  
I
50  
A
OUT  
V
V
IL  
or V  
IN  
OH  
OH  
IH  
4.5  
5.5  
4.5  
5.5  
3.86  
4.86  
0.1  
3.76  
4.76  
0.1  
V
V
V
A
I
I
=
=
24 mA  
24 mA (Note 2)  
V
Maximum LOW  
Output Voltage  
0.001  
0.001  
OL  
I
50  
A
OUT  
0.1  
0.1  
V
V
or V  
IH  
IN  
OL  
OL  
IL  
4.5  
5.5  
0.36  
0.36  
0.44  
0.44  
I
I
= 24 mA  
= 24 mA (Note 2)  
I
I
Maximum I/O  
V
V
V
, V  
IH  
OZT  
IN  
I
IL  
5.5  
0.5  
0.1  
5.0  
Leakage Current  
Maximum Input  
Leakage Current  
V
, GND  
O
CC  
5.5  
5.5  
5.5  
5.5  
1.0  
1.5  
A
mA  
A
V
V
V
V
V
, GND  
2.1V  
I
CC  
CC  
I
I
Maximum I /Input  
CC  
0.6  
CCT  
CC  
I
Max Quiescent  
8.0  
80.0  
V
or GND  
IN  
CC  
Supply Current  
I
I
Minimum Dynamic  
Output Current (Note 3)  
75  
75  
mA  
mA  
V
V
1.65V Max  
3.85V Min  
OLD  
OHD  
OLD  
OHD  
Note 2: All outputs loaded; thresholds associated with output under test.  
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.  
3
www.fairchildsemi.com  
AC Electrical Characteristics  
V
T
25 C  
T
40 C to 85 C  
50 pF  
Min Max  
CC  
A
A
C
50 pF  
C
L
Symbol  
Parameter  
(V)  
(Note 4)  
5.0  
Units  
L
Min  
3.2  
2.6  
3.7  
4.1  
2.2  
2.0  
Typ  
Max  
8.4  
t
Propagation  
Delay A , B to B , A  
n
5.7  
5.1  
6.4  
7.4  
5.4  
5.2  
3.2  
2.6  
2.7  
3.4  
2.2  
2.0  
9.0  
8.4  
PLH  
ns  
ns  
ns  
t
7.9  
PHL  
n
n
n
t
Output Enable  
Time  
5.0  
5.0  
9.4  
10.0  
11.6  
9.3  
PZH  
t
10.5  
8.7  
PZL  
t
Output Disable  
Time  
PHZ  
t
8.2  
8.8  
PLZ  
Note 4: Voltage Range 5.0 is 5.0V 0.5V.  
Capacitance  
Symbol  
Parameter  
Typ  
4.5  
25  
Units  
pF  
Conditions  
C
C
Input Pin Capacitance  
V
V
5.0V  
5.0V  
IN  
CC  
CC  
Power Dissipation Capacitance  
pF  
PD  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
Package Number MS48A  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Package Number MTD48  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
6

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