74ACT16373SSC_NL [FAIRCHILD]
Bus Driver, ACT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48;
| 型号： | 74ACT16373SSC_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ACT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1999
Revised May 2005
74ACT16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
Features
The ACT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is low, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
■ Separate control logic for each byte
■ 16-bit version of the ACT373
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Order Number
74ACT16373SSC
74ACT16373MTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active Low)
LEn
Latch Enable Input
Inputs
I0–I15
O0–O15
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500297
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Functional Description
Truth Tables
The ACT16373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
Inputs
OE1
Outputs
O0–O7
LE1
I0–I7
X
H
H
L
H
L
L
L
X
L
Z
L
H
the Dn enters the latches. In this condition the latches are
H
X
transparent, i.e., a latch output will change states each time
its D input changes. When LEn is LOW, the latches store
(Previous)
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The
Inputs
OE2
Outputs
O8–O15
3-STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
LE2
I8–I15
puts are in the 2-state mode. When OEn is HIGH, the stan-
X
H
H
L
H
L
L
L
X
L
Z
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
L
H
H
X
(Previous)
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
VI VCC 0.5V
DC Output Diode Current (IOK
VO 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
20 mA
20 mA
Input Voltage (VI)
Output Voltage (VO)
0V to VCC
)
Operating Temperature (TA)
40 C to 85 C
125 mV/ns
20 mA
20 mA
Minimum Input Edge Rate ( V/ t)
VO VCC 0.5V
V
IN from 0.8V to 2.0V
DC Output Voltage (VO)
0.5V to VCC 0.5V
50 mA
VCC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Note 1: Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
50 mA
Junction Temperature
140 C
Storage Temperature
65 C to 150 C
DC Electrical Characteristics
V
T
25 C
T
A
40 C to 85 C
Symbol
Parameter
Units
Conditions
CC
A
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
IH
OUT
V
V
V
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
1.5
2.0
0.8
0.8
4.4
5.4
or V
0.1V
0.1V
0.1V
CC
1.5
V
IL
OUT
1.5
or V
CC
4.49
5.49
OH
I
50
A
OUT
V
V
IL
or V
IN
OH
OH
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
24 mA
24 mA (Note 2)
V
Maximum LOW
Output Voltage
0.001
0.001
OL
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
0.36
0.36
0.44
0.44
I
I
24 mA
24 mA (Note 2)
I
I
Maximum 3-STATE
Leakage Current
Maximum Input
V
V
V
, V
IH
OZ
I
IL
5.5
5.5
0.5
0.1
5.0
1.0
A
A
V
, GND
O
CC
IN
V
V
V
, GND
2.1V
I
CC
Leakage Current
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
0.6
1.5
80.0
75
mA
A
V
V
V
V
CCT
CC
I
CC
Max Quiescent Supply Current
Minimum Dynamic
8.0
V
or GND
IN
CC
mA
mA
1.65V Max
3.85V Min
OLD
OHD
OLD
OHD
Output Current (Note 3)
75
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
3
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AC Electrical Characteristics
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 4)
5.0
Units
L
Min
3.1
2.6
3.1
2.8
2.5
2.7
2.1
2.0
Typ
Max
7.9
7.3
7.9
7.3
7.4
7.5
7.9
7.4
t
Propagation Delay
D to O
n
5.3
4.6
5.4
4.9
4.7
4.8
5.1
4.5
3.1
2.6
3.2
2.8
2.5
2.7
2.1
2.0
8.4
7.8
8.4
7.8
7.9
8.0
8.2
7.9
PLH
ns
ns
ns
ns
t
PHL
n
t
Propagation Delay
LE to O
5.0
5.0
5.0
PLH
t
PHL
n
t
Output Enable
Delay
PZH
t
PZL
t
Output Disable
Delay
PHZ
t
PLZ
Note 4: Voltage Range 5.0 is 5.0V 0.5V.
AC Operating Requirements
V
T
25 C
T
A
40 C to 85 C
50 pF
CC
A
C
50 pF
C
Units
Symbol
Parameter
(V)
L
L
(Note 5)
Guaranteed Minimum
t
Setup Time, HIGH or
S
5.0
3.0
1.5
4.0
3.0
ns
ns
ns
LOW, Input to Clock
Hold time, HIGH or
LOW, Input to Clock
CS Pulse Width,
HIGH or LOW
t
t
H
W
5.0
5.0
1.5
4.0
Note 5: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
30
Units
pF
Conditions
C
C
Input Capacitance
V
V
5.0V
5.0V
IN
CC
CC
Power Dissipation Capacitance
pF
PD
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4
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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