74ACT18823SSC [FAIRCHILD]
18-Bit D-Type Flip-Flop with 3-STATE Outputs; 18位D型触发器带3态输出
| 型号： | 74ACT18823SSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 18-Bit D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1999
Revised October 1999
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
■ Broadside pinout allows for easy board layout
■ Separate control logic for each byte
■ Extra data width for wider address/data paths or buses
carrying parity
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Order Number
74ACT18823SSC
74ACT18823MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
CLRn
ENn
CPn
I0–I17
O0–O17
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500294
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Functional Description
Function Table
(Note 1)
The ACT18823 consists of eighteen D-type edge-triggered
flip-flops. These have 3-STATE outputs for bus systems
organized with inputs and outputs on opposite sides. The
device is byte controlled with each byte functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The follow-
ing description applies to each byte. The buffered clock
(CPn) and buffered Output Enable (OEn) are common to all
Inputs
Internal Output
Function
OE CLR EN CP
In
Q
On
H
H
H
L
X
X
L
L
L
L
H
X
X
X
X
L
L
H
Z
Z
High Z
High Z
Clear
Clear
Hold
flip-flops within that byte. The flip-flops will store the state
of their individual D inputs that meet set-up and hold time
requirements on the LOW-to-HIGH CPn transition. With
X
X
H
H
L
X
X
X
X
L
Z
L
L
L
OEn LOW, the contents of the flip-flops are available at the
outputs. When OEn is HIGH, the outputs go to the imped-
ance state. Operation of the OEn input does not affect the
H
L
H
H
H
H
H
H
NC
NC
L
Z
NC
Z
Hold
H
H
L
Load
Load
Load
Load
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLRn) and Clock Enable
L
H
L
H
Z
(ENn) pins. These devices are ideal for parity bus interfac-
ing in high performance systems.
L
L
L
L
L
H
H
H
When CLRn is LOW and OEn is LOW, the outputs are
LOW. When CLRn is HIGH, data can be entered into the
flip-flops. When ENn is LOW, data on the inputs is trans-
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
= LOW-to-HIGH Transition
NC= No Change
ferred to the outputs on the LOW-to-HIGH clock transition.
When the ENn is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Note 1: The table represents the logic for one byte. The two bytes are inde-
pendent of each other and function identically.
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC +0.5V
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
V
V
O = −0.5V
−20 mA
+20 mA
O = VCC +0.5V
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
± 50 mA
V
CC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Per Output Pin
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
± 50 mA
Junction Temperature
PDIP/SOIC
+140°C
Storage Temperature
−65°C to +150°C
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
Minimum HIGH
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
= 0.1V
IH
OUT
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or V −0.1V
CC
V
Maximum LOW
Input Voltage
1.5
V
= 0.1V
IL
OUT
1.5
or V −0.1V
CC
V
Minimum HIGH
Output Voltage
4.49
5.49
OH
I
= −50 µA
OUT
V
= V or V
IN
OH
OH
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
= −24 mA
= −24 mA (Note 3)
V
Maximum LOW
Output Voltage
0.001
0.001
OL
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
V
I
I
= 24 mA
= 24 mA (Note 3)
I
Maximum 3-STATE
V = V , V
OZ
I
IL
IH
5.5
±0.5
±0.1
±5.0
µA
Leakage Current
V
= V , GND
O
CC
I
I
I
I
I
Maximum Input Leakage Current
5.5
5.5
5.5
±1.0
1.5
µA
mA
µA
V = V , GND
I CC
IN
Maximum I /Input
CC
0.6
V = V −2.1V
CCT
CC
I
CC
Maximum Quiescent Supply Current
Minimum Dynamic
8.0
80.0
75
V
V
V
= V or GND
CC
IN
mA
mA
= 1.65V Max
= 3.85V Min
OLD
OHD
OLD
OHD
5.5
Output Current (Note 4)
−75
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 5)
Min
Max
Min
Max
f
Maximum Clock
Frequency
MAX
5.0
5.0
5.0
5.0
5.0
100
90
MHz
ns
t
t
t
Propagation Delay
CP to O
2.0
2.0
9.0
9.0
2.0
2.0
9.5
9.5
PHL
PLH
PHL
n
n
Propagation Delay
CLR to O
2.0
9.0
2.0
9.5
ns
n
n
t
t
t
t
Output Enable Time
2.0
2.0
1.5
1.5
9.0
9.0
7.0
8.0
2.0
2.0
1.5
1.5
10.0
10.0
7.5
PZL
PZH
PLZ
PHZ
ns
Output Disable Time
ns
8.5
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 6)
Guaranteed Minimum
t
t
t
t
Setup Time, HIGH or LOW,
Input to Clock
S
5.0
5.0
5.0
5.0
3.0
3.0
1.5
3.0
1.5
ns
ns
ns
ns
Hold Time, HIGH or LOW,
Input to Clock
H
S
H
1.5
3.0
1.5
Setup Time, HIGH or LOW,
Enable to Clock
Hold Time, HIGH or LOW,
Enable to Clock
t
CP Pulse Width,
n
W
5.0
4.0
4.0
ns
HIGH or LOW
t
t
CLR Pulse Width,
n
W
5.0
5.0
4.0
6.0
4.0
6.0
ns
ns
HIGH or LOW
Recovery Time,
rec
CLR to CP
n
n
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
C
Input Pin Capacitance
4.5
95
pF
pF
V
V
= 5.0V
IN
CC
CC
Power Dissipation Capacitance
= 5.0V
PD
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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