74ACT18825MTD [FAIRCHILD]

18-Bit Buffer/Line Driver with 3-STATE Outputs; 18位与3态输出缓冲器/线路驱动器


型号：	74ACT18825MTD
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	18-Bit Buffer/Line Driver with 3-STATE Outputs 18位与3态输出缓冲器/线路驱动器驱动器
文件：	总6页 (文件大小：51K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

August 1999

Revised October 1999

74ACT18825

18-Bit Buffer/Line Driver with 3-STATE Outputs

General Description

Features

The ACT18825 contains eighteen non-inverting buffers

with 3-STATE outputs designed to be employed as a mem-

ory and address driver, clock driver, or bus oriented trans-

mitter/receiver. The device is byte controlled. Each byte

has separate 3-STATE control inputs which can be shorted

together for full 18-bit operation.

■ Broadside pinout allows for easy board layout

■ Separate control logic for each byte

■ Extra data width for wider address/data paths or buses

carrying parity

■ Outputs source/sink 24 mA

■ TTL-compatible inputs

Ordering Code:

Order Number

74ACT18825SSC

74ACT18825MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

Description

OE_n

Output Enable Input (Active LOW)

I₀–I₁₇

O₀–O₁₇

Inputs

Outputs

FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

DS0500292

www.fairchildsemi.com

Functional Description

Truth Table

The ACT18825 contains eighteen non-inverting buffers

with 3-STATE standard outputs. The device is byte con-

trolled with each byte functioning identically, but indepen-

dently of the other. The control pins may be shorted

together to obtain full 8-bit operation. The 3-STATE outputs

are controlled by an Output Enable (OE_n) input for each

Inputs

Outputs

Byte 1 (0:8) Byte 2 (8:17)

I₀–I₈I₉–I₁₇O₀–O₈O₉–O₁₇

OE₁OE₂OE₃OE₄

byte. When OE_nis LOW, the outputs are in 2-state mode.

When OE_nis HIGH, the outputs are in the high impedance

mode, but this does not interfere with entering new data

into the inputs.

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = HIGH Impedance

Logic Diagram

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Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

Supply Voltage (V_CC

)

−0.5V to +7.0V

DC Input Diode Current (I_IK

V_I= −0.5V

)

Supply Voltage (V_CC

)

4.5V to 5.5V

0V to V_CC

−20 mA

+20 mA

Input Voltage (V_I)

V_I= V_CC+0.5V

Output Voltage (V_O)

0V to V_CC

DC Output Diode Current (I_OK

)

Operating Temperature (T_A)

Minimum Input Edge Rate (∆V∆t)

V_INfrom 0.8V to 2.0V

−40°C to +85°C

125 mV/ns

_O= −0.5V

−20 mA

+20 mA

_O= V_CC+0.5V

DC Output Voltage (V_O)

−0.5V to V_CC+ 0.5V

±50 mA

_CC@ 4.5V, 5.5V

DC Output Source/Sink Current (I_O)

DC V_CCor Ground Current

Per Output Pin

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, temperature, and output/input loading variables. Fairchild does not

recommend operation of FACT circuits outside databook specifications.

±50 mA

Storage Temperature

−65°C to +150°C

DC Electrical Characteristics

= +25°C

T = −40°C to +85°C

Symbol

Parameter

Units

Conditions

(V)

4.5

5.5

4.5

5.5

4.5

5.5

Typ

1.5

Guaranteed Limits

Minimum HIGH

2.0

0.8

4.4

5.4

= 0.1V

OUT

Input Voltage

Maximum LOW

Input Voltage

Minimum HIGH

Output Voltage

1.5

2.0

0.8

4.4

5.4

or V −0.1V

1.5

= 0.1V

OUT

1.5

or V −0.1V

4.49

5.49

= −50 µA

OUT

= V or V

4.5

5.5

4.5

5.5

3.86

4.86

0.1

3.76

4.76

0.1

= −24 mA

= −24 mA (Note 2)

Maximum LOW

Output Voltage

0.001

= 50 µA

OUT

0.1

= V or V

4.5

5.5

0.36

0.44

= 24 mA

= 24 mA (Note 2)

Maximum 3-STATE

V = V , V

5.5

±0.5

±5.0

µA

Leakage Current

= V , GND

Maximum Input Leakage Current

5.5

± 0.1

± 1.0

1.5

µA

V = V , GND

I CC

Maximum I /Input

0.6

V = V −2.1V

CCT

Maximum Quiescent Supply Current

Minimum Dynamic

8.0

80.0

= V or GND

= 1.65V Max

= 3.85V Min

OLD

OHD

OLD

OHD

5.5

Output Current (Note 3)

−75

Note 2: All outputs loaded; thresholds associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

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AC Electrical Characteristics

= +25°C

= 50 pF

T = −40°C to +85°C

C = 50 pF

Symbol

Parameter

(V)

Units

(Note 4)

Min

2.0

1.5

Typ

5.3

5.6

6.3

6.5

4.5

5.1

Max

8.4

8.7

9.6

9.7

7.3

8.5

Min

Max

Propagation Delay

2.0

1.5

9.0

9.2

PHL

5.0

Data to Output

Output Enable

Time

PLH

PZL

PZH

PLZ

PHZ

10.3

10.4

7.6

Output Disable

Time

8.8

Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.

Capacitance

Symbol

Parameter

Typ

4.5

Units

Conditions

Input Pin Capacitance

= 5.0V

Power Dissipation Capacitance

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Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

Package Number MS56A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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