74ACT323PCQR [FAIRCHILD]
Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, PDIP20, PLASTIC, DIP-20;
| 型号： | 74ACT323PCQR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, PDIP20, PLASTIC, DIP-20 存储 |
| 文件： | 总6页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1988
Revised October 1998
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
Features
■ ICC and IOZ reduced by 50%
The ACT323 is an 8-bit universal shift/storage register with
3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q0 and Q7 to allow
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load and
store
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT323PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP
Pin Descriptions
Pin Name
CP
Description
Clock Pulse Input
DS0
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
DS7
S0, S1
SR
Synchronous Reset Input
3-STATE Output Enable Inputs
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
Serial Outputs
OE1, OE2
I/O0–I/O7
Q0, Q7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009787.prf
www.fairchildsemi.com
Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S0 and S1 as shown
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
A HIGH signal on either OE1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S0 and S1 in preparation for a paral-
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
lel load operation.
Mode Select Table
Inputs
Response
SR
S1
S0
CP
L
H
H
H
H
X
H
L
X
H
H
L
Synchronous Reset; Q0–Q7 = LOW
Parallel Load; I/On→Qn
Shift Right; DS0→Q0, Q0→Q1, etc.
Shift Left; DS7→Q7, Q7→Q6, etc.
Hold
H
L
L
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Junction Temperature (TJ)
PDIP
Absolute Maximum Ratings(Note 1)
140°C
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Recommended Operating
Conditions
−20 mA
+20 mA
VI = VCC + 0.5V
Supply Voltage (VCC
Input Voltage (VI)
)
4.5V to 5.5V
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
DC Output Diode Current (IOK
O = −0.5V
)
Output Voltage (VO)
0V to VCC
V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
−40°C to +85°C
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source or
Sink Current (IO)
−0.5V to V CC + 0.5V
VCC @ 4.5V, 5.5V
125 mV/ns
±50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC VCC or Ground Current
Per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
)
−65°C to +150°C
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to +85°C
A
Symbol
Parameter
Units
Conditions
CC
A
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
V
= 0.1V
IH
OUT
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
Maximum Low Level
Input Voltage
V
= 0.1V
IL
OUT
or V − 0.1V
CC
Minimum High Level
Output Voltage
4.49
5.49
I
= −50 µA
OH
OUT
V
= V or V
IN
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
I
= −24 mA
OH
OH
OUT
= −24 mA (Note 2)
V
Maximum Low Level
Output Voltage
0.001
0.001
= 50 µA
OL
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
V
I
I
= −24 mA
= −24 mA (Note 2)
I
I
Maximum Input
Leakage Current
Maximum I/O
µA
µA
V = V , GND
IN
I
CC
5.5
±0.3
±3.0
V
V
= V or GND
CC
OZT
I/O
Leakage Current
= V , V
IH IL
IN
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
µA
V = V − 2.1V
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
V
V
V
= 1.65V Max
OLD
OHD
−75
40.0
= 3.85V Min
4.0
= V or GND
CC
IN
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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4
AC Electrical Characteristics
V
T
= 25°C
T = −40°C to +85°C
A
CC
A
C
= 50 pF
C = 50 pF
L
Symbol
Parameter
(V)
(Note 4)
5.0
Units
L
Min
120
5.0
Typ
125
9.0
Max
12.5
13.5
12.5
14.5
Min
110
Max
f
Maximum Input Frequency
Propagation Delay
MHz
ns
max
t
5.0
4.0
4.5
4.5
5.0
14.0
15.0
14.5
16.0
PLH
CP to Q or Q
0
7
t
t
t
Propagation Delay
CP to Q or Q
5.0
5.0
5.0
5.0
5.0
6.0
9.0
8.5
ns
ns
ns
PHL
PLH
PHL
0
7
Propagation Delay
CP to I/O
n
Propagation Delay
CP to I/O
10.0
n
t
t
t
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
3.5
3.5
4.0
3.0
7.5
7.5
8.5
8.0
11.0
11.5
12.5
11.5
3.0
3.0
3.0
2.5
12.5
13.0
13.5
12.5
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
Note 4: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
T
= 25°C
= 50 pF
= +5.0V
T = −40°C to +85°C
A
A
C
C
= 50 pF
= +5.0V
Symbol
Parameter
V
Units
L
L
CC
V
V
CC
(V)
CC
(Note 5)
Typ
Guaranteed Minimum
t
t
t
t
t
t
t
Setup Time, HIGH or LOW
5.0
2.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
S
H
S
H
S
H
W
S
or S to CP
1
0
Hold Time, HIGH or LOW
or S to CP
5.0
5.0
5.0
5.0
5.0
5.0
0
1.0
0
1.5
4.0
1.0
2.5
1.0
4.0
1.5
4.5
1.0
2.5
1.0
4.5
S
0
1
Setup Time, HIGH or LOW
I/O , DS , DS to CP
n
0
7
Hold Time, HIGH or LOW
I/O , DS , DS to CP
n
0
7
Setup Time, HIGH or LOW
SR to CP
1.0
0
Hold Time, HIGH or LOW
SR to CP
CP Pulse Width
HIGH or LOW
2.0
Note 5: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
Units
Conditions
C
pF
pF
V
V
= OPEN
= 5.0V
IN
CC
CC
C
170
PD
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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