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74ACT323SC [NSC]

ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, SOIC-20;
74ACT323SC
型号： 74ACT323SC
厂家： National Semiconductor    National Semiconductor
描述：

ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, SOIC-20

光电二极管 输出元件
文件： 总8页 (文件大小：183K)
中文：  中文翻译
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March 1993  
54ACT/74ACT323  
8-Bit Universal Shift/Storage Register  
with Synchronous Reset and Common I/O Pins  
General Description  
The ’ACT323 is an 8-bit universal shift/storage register with  
Features  
Y
I
and I  
reduced by 50%  
OZ  
CC  
Common parallel I/O for reduced pin count  
Y
Y
Y
TRI-STATE outputs. Parallel load inputs and flip-flop out-  
É
puts are multiplexed to minimize pin count. Separate serial  
inputs and outputs are provided for Q and Q to allow easy  
Additional serial inputs and outputs for expansion  
Four operating modes: shift left, shift right, load and  
store  
0
7
cascading. Four operation modes are possible: hold (store),  
shift left, shift right and parallel load.  
Y
Y
Y
Y
TRI-STATE outputs for bus-oriented applications  
Outputs source/sink 24 mA  
TTL-compatible inputs  
Standard Military Drawing (SMD)  
Ð ’ACT323: 5962-91607  
Logic Symbols  
Connection Diagrams  
Pin Assignment for  
DIP, SOIC and Flatpak  
TL/F/9787–1  
TL/F/9787–2  
Pin Assignment  
for LCC  
TL/F/9787–5  
Pin Name  
Description  
Clock Pulse Input  
CP  
DS  
DS  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
Mode Select Inputs  
0
7
S , S  
0
1
SR  
Synchronous Reset Input  
TRI-STATE Output Enable Inputs  
Multiplexed Parallel Data Inputs or  
TRI-STATE Parallel Data Outputs  
Serial Outputs  
OE , OE  
1
2
I/O –I/O  
0
7
TL/F/9787–3  
Q , Q  
0
7
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9787  
RRD-B30M115/Printed in U. S. A.  
Functional Description  
The ’ACT323 contains eight edge-triggered D-type flip-flops  
and the interstage logic necessary to perform synchronous  
reset, shift left, shift right, parallel load and hold operations.  
All other state changes are also initiated by the LOW-to-  
HIGH CP transition. Inputs can change when the clock is in  
either state provided only that the recommended setup and  
hold times, relative to the rising edge of CP, are observed.  
The type of operation is determined by S and S as shown  
1
0
in the Mode Select Table. All flip-flop outputs are brought  
out through TRI-STATE buffers to separate I/O pins that  
also serve as data inputs in the parallel load mode. Q and  
A
HIGH signal on either OE or OE disables the  
1 2  
TRI-STATE buffers and puts the I/O pins in the high imped-  
ance state. In this condition the shift, load, hold and reset  
operations can still occur. The TRI-STATE buffers are also  
0
Q
are also brought out on other pins for expansion in serial  
shifting of longer words.  
7
disabled by HIGH signals on both S and S in preparation  
1
0
A LOW signal on SR overrides the Select inputs and allows  
the flip-flops to be reset by the next rising edge of CP.  
for a parallel load operation.  
Mode Select Table  
Inputs  
Response  
SR  
S
1
S
0
CP  
e
LOW  
L
H
H
H
H
X
X
L
L
L
L
X
Synchronous Reset; Q –Q  
0
7
H
L
H
H
L
Parallel Load; I/Onx  
0
Q
Shift Right; DS0xQ , Qn0xQ , etc.  
1
H
L
Shift Left; DS7xQ , Q7xQ , etc.  
7
6
L
Hold  
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
e
L
LOW-to-HIGH Clock Transition  
2
Logic Diagram  
TL/F/9787–4  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
3
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
Recommended Operating  
Conditions  
Supply Voltage (V  
’ACT  
)
CC  
4.5V to 5.5V  
b
a
0.5V to 7.0V  
Supply Voltage (V  
)
CC  
Input Voltage (V )  
I
0V to V  
0V to V  
CC  
DC Input Diode Current (I  
)
IK  
Output Voltage (V  
)
O
CC  
e b  
b
a
V
I
V
I
0.5V  
a
20 mA  
20 mA  
Operating Temperature (T )  
A
e
V
CC  
0.5V  
b
b
a
40 C to 85 C  
74ACT  
54ACT  
§
55 C to 125 C  
§
§
b
b
a
0.5V  
DC Input Voltage (V )  
I
0.5V to V  
0.5V to V  
CC  
a
§
DC Output Diode Current (I  
)
OK  
Minimum Input Edge Rate (DV/Dt)  
’ACT Devices  
e b  
b
a
V
V
0.5V  
a
20 mA  
20 mA  
O
O
e
V
CC  
0.5V  
V
V
from 0.8V to 2.0V  
@
IN  
a
DC Output Voltage (V  
DC Output Source or  
)
O
0.5V  
50 mA  
50 mA  
CC  
4.5V, 5.5V  
125 mV/ns  
CC  
g
g
Sink Current (I  
)
O
DC V  
or Ground Current  
CC  
Per Output Pin (I or I  
CC  
)
GND  
)
b
a
65 C to 150 C  
Storage Temperature (T  
§
§
STG  
Junction Temperature (T )  
J
CDIP  
PDIP  
175 C  
§
140 C  
§
Note 1: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, without  
exception, to ensure that the system design is reliable over its power supply,  
temperature, and output/input loading variables. National does not recom-  
mend operation of FACTTM circuits outside databook specifications.  
DC Electrical Characteristics for ’ACT Family Devices  
54ACT  
74ACT  
74ACT  
e
e
T
A
V
CC  
(V)  
T
A
55 C to 125 C  
e a  
Symbol  
Parameter  
T
25 C  
§
Units  
Conditions  
A
b
a
b a  
40 C to 85 C  
§
§
§
Guaranteed Limits  
§
Typ  
e
0.1V  
V
V
V
Minimum High Level  
Input Voltage  
4.5  
5.5  
1.5  
1.5  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
V
IH  
OUT  
V
V
V
b
or V  
CC  
0.1V  
e
Maximum Low Level  
Input Voltage  
4.5  
5.5  
1.5  
1.5  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
V
OUT  
0.1V  
0.1V  
IL  
b
or V  
CC  
e b  
OUT  
Minimum High Level  
Output Voltage  
4.5  
5.5  
4.49  
5.49  
4.4  
5.4  
4.4  
5.4  
4.4  
5.4  
I
50 mA  
OH  
e
*V  
IN  
OH  
V
IL  
or V  
IH  
b
b
4.5  
5.5  
3.86  
4.86  
3.70  
4.70  
3.76  
4.76  
I
24 mA  
24 mA  
V
V
e
e
V
OL  
Maximum Low Level  
Output Voltage  
4.5 0.001  
5.5 0.001  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
I
50 mA  
OUT  
*V  
V or V  
IL IH  
IN  
b
b
4.5  
5.5  
0.36  
0.36  
0.50  
0.50  
0.44  
0.44  
I
24 mA  
24 mA  
OL  
V
e
I
I
Maximum Input  
Leakage Current  
V
V
, GND  
IN  
I
CC  
g
g
g
g
g
g
5.5  
5.5  
0.1  
0.3  
1.0  
5.5  
1.0  
3.0  
mA  
mA  
e
V
Maximum I/O  
Leakage Current  
V
V
V
or GND  
OZT  
I/O  
CC  
, V  
e
IN  
IH IL  
e
b
2.1V  
I
I
I
I
Maximum I /Input  
CC  
5.5  
0.6  
1.6  
50  
1.5  
75  
mA  
mA  
mA  
V
V
V
V
V
CC  
CCT  
OLD  
OHD  
CC  
I
e
²
Minimum Dynamic Output 5.5  
1.65V Max  
e
3.85V Min  
OLD  
OHD  
Current  
b
b
5.5  
5.5  
50  
75  
e
Maximum Quiescent  
Supply Current  
V
or GND  
IN  
CC  
4.0  
80.0  
40.0  
mA  
*All outputs loaded; thresholds on input associated with output under test.  
²
Maximum test duration 2.0 ms, one output loaded at a time.  
@
for 54ACT is identical to 74ACT 25 C.  
Note: I  
§
CC  
4
AC Electrical Characteristics  
74ACT  
54ACT  
e b  
74ACT  
e b  
40 C  
T
55 C  
T
§
to 125 C  
§
A
A
e
e
V *  
CC  
(V)  
T
25 C  
§
50 pF  
A
a
e
a
e
Symbol  
Parameter  
to 85 C  
Units  
§
50 pF  
§
50 pF  
C
L
C
C
L
L
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
f
t
Maximum Input Frequency  
Propagation Delay  
5.0  
5.0  
120  
125  
70  
110  
MHz  
ns  
max  
PLH  
5.0  
5.0  
5.0  
6.0  
9.0  
9.0  
12.5  
13.5  
12.5  
14.5  
1.0  
1.0  
1.0  
1.0  
16.5  
17.0  
16.5  
18.0  
4.0  
4.5  
4.5  
5.0  
14.0  
15.0  
14.5  
16.0  
CP to Q or Q  
0
7
t
t
t
Propagation Delay  
CP to Q or Q  
PHL  
PLH  
PHL  
5.0  
5.0  
5.0  
ns  
ns  
ns  
0
7
Propagation Delay  
CP to I/O  
8.5  
n
Propagation Delay  
CP to I/O  
10.0  
n
t
t
t
t
Output Enable Time  
Output Enable Time  
Output Disable Time  
Output Disable Time  
5.0  
5.0  
5.0  
5.0  
3.5  
3.5  
4.0  
3.0  
7.5  
7.5  
8.5  
8.0  
11.0  
11.5  
12.5  
11.5  
1.0  
1.0  
1.0  
1.0  
15.5  
15.5  
15.5  
15.0  
3.0  
3.0  
3.0  
2.5  
12.5  
13.0  
13.5  
12.5  
ns  
ns  
ns  
ns  
PZH  
PZL  
PHZ  
PLZ  
g
*Voltage Range 5.0 is 5.0V 0.5V  
AC Operating Requirements  
74ACT  
54ACT  
e b  
74ACT  
e b  
40 C  
T
55 C  
T
§
to 125 C  
§
A
A
e
e
T
25 C  
§
50 pF  
A
a
a
to 85 C  
V *  
CC  
(V)  
§
§
Symbol  
Parameter  
C
Units  
L
e
e
50 pF  
C
50 pF  
e a  
C
L
L
e a  
V
5.0V  
CC  
e a  
5.0V  
V
5.0V  
V
CC  
CC  
Typ  
Guaranteed Minimum  
t
t
t
t
t
t
t
Setup Time, HIGH or LOW  
s
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
2.0  
5.0  
1.5  
4.0  
1.0  
2.5  
1.0  
4.0  
6.0  
5.0  
1.5  
4.5  
1.0  
2.5  
1.0  
4.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
S
0
or S to CP  
1
Hold Time, HIGH or LOW  
or S to CP  
h
s
0
1.0  
0
2.0  
4.5  
2.5  
3.0  
1.5  
5.0  
S
0
1
Setup Time, HIGH or LOW  
I/O , DS , DS to CP  
n
0
7
Hold Time, HIGH or LOW  
I/O , DS , DS to CP  
h
s
n
0
7
Setup Time, HIGH or LOW  
SR to CP  
1.0  
0
Hold Time, HIGH or LOW  
SR to CP  
h
w
CP Pulse Width  
HIGH or LOW  
2.0  
g
*Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Power Dissipation Capacitance  
Typ  
Units  
Conditions  
e
e
C
C
4.5  
pF  
pF  
V
V
OPEN  
5.0V  
IN  
CC  
170  
PD  
CC  
5
Ordering Information  
The device number is used to form part of a simplified purchasing code where the package type and temperature range are  
defined as follows:  
74ACT 323  
P
C
QR  
Temperature Range Family  
Special Variations  
e
e
e
e
74ACT  
54ACT  
Commercial TTL-Compatible  
Military TTL-Compatible  
X
QR  
Devices shipped in 13 reels  
×
Commercial grade device with  
burn-in  
Device Type  
e
QB  
Military grade device with  
environmental and burn-in  
processing shipped in tubes  
Package Code  
e
e
e
e
e
P
D
F
L
Plastic DIP  
Ceramic DIP  
Flatpak  
Leadless Chip Carrier (LCC)  
Small Outline (SOIC)  
Temperature Range  
e
e
C
M
Commercial  
Military  
S
Physical Dimensions inches (millimeters)  
20 Terminal Ceramic Leadless Chip Carrier (L)  
NS Package Number E20A  
6
Physical Dimensions inches (millimeters) (Continued)  
20 Lead Ceramic Dual-In-Line Package (D)  
NS Package Number J20A  
20 Lead Small Outline Integrated Circuit (S)  
NS Package Number M20B  
7
Ý
Lit. 114679  
Physical Dimensions inches (millimeters) (Continued)  
20 Lead Plastic Dual-In-Line Package (P)  
NS Package Number N20B  
20 Lead Ceramic Flatpak (F)  
NS Package Number W20A  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant  
into the body, or (b) support or sustain life, and whose  
failure to perform, when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
National Semiconductor  
Corporation  
National Semiconductor  
Europe  
National Semiconductor  
Hong Kong Ltd.  
National Semiconductor  
Japan Ltd.  
a
1111 West Bardin Road  
Arlington, TX 76017  
Tel: 1(800) 272-9959  
Fax: 1(800) 737-7018  
Fax:  
(
49) 0-180-530 85 86  
@
13th Floor, Straight Block,  
Ocean Centre, 5 Canton Rd.  
Tsimshatsui, Kowloon  
Hong Kong  
Tel: (852) 2737-1600  
Fax: (852) 2736-9960  
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a
a
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a
Deutsch Tel:  
English Tel:  
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Italiano Tel:  
(
(
(
(
49) 0-180-530 85 85  
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49) 0-180-534 16 80  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.  

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