74ACT373SC [FAIRCHILD]
Octal Transparent Latch with 3-STATE Outputs; 八路透明锁存器具有三态输出
| 型号： | 74ACT373SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Transparent Latch with 3-STATE Outputs |
| 文件： | 总10页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC373 • 74ACT373
Octal Transparent Latch with 3-STATE Outputs
General Description
Features
The AC/ACT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC373SC
74AC373SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC373MTC
74AC373PC
74ACT373SC
74ACT373SJ
74ACT373MSA
74ACT373MTC
74ACT373PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MSA20
MTC20
N20A
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
LE
Data Inputs
Latch Enable Input
OE
Output Enable Input
3-STATE Latch Outputs
O0–O7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009958
www.fairchildsemi.com
Functional Description
Truth Table
The AC/ACT373 contains eight D-type latches with 3-
STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
Inputs
Outputs
On
LE
OE
Dn
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D-type input changes.
When LE is LOW, the latches store the information that
was present on the D-type inputs a setup time preceding
the HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2-state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
T
A = +25°C
TA = −40°C to +85°C
VCC
(V)
Symbol
VIH
Parameter
Units
Conditions
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
V
IN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OL = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
3.0
4.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current
µA
µA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, GND
IOZ
Maximum 3-STATE Current
5.5
±0.25
± 2.5
V
O = VCC, GND
IOLD
Minimum Dynamic Output Current
(Note 3)
5.5
75
mA
V
OLD = 1.65V Max
IOHD
ICC (Note 4) Maximum Quiescent Supply Current
5.5
5.5
−75
mA
V
V
OHD = 3.85V Min
IN = VCC or GND
4.0
40.0
µA
Note 2: All outputs loaded, thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
www.fairchildsemi.com
DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH= −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
5.5
5.5
± 0.1
± 1.0
± 2.5
µA
µA
VI = VCC, GND
VI = VIL, VIH
Leakage Current
Maximum 3-STATE
Current
IOZ
± 0.25
VO = VCC, GND
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
VI = VCC − 2.1V
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
−75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Typ
10.0
7.0
9.5
7.0
10.0
7.5
9.5
7.0
9.0
7.0
8.5
6.5
10.0
8.0
8.0
6.5
Max
13.5
9.5
Min
tPLH
Propagation Delay
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
15.0
10.5
14.5
10.5
15.0
10.5
14.0
10.5
13.0
9.5
ns
ns
ns
ns
ns
ns
ns
ns
Dn to On
5.0
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Dn to On
3.3
13.0
9.5
5.0
Propagation Delay
LE to On
3.3
13.5
9.5
5.0
Propagation Delay
LE to On
3.3
12.5
9.5
5.0
Output Enable Time
3.3
11.5
8.5
5.0
Output Enable Time
Output Disable Time
Output Disable Time
3.3
11.5
8.5
13.0
9.5
5.0
3.3
12.5
11.0
11.5
8.5
14.5
12.5
12.5
10.0
5.0
3.3
5.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Operating Requirements for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
tS
Setup Time, HIGH or LOW
Dn to LE
3.5
2.0
5.5
6.0
4.5
1.0
1.0
6.0
4.5
ns
ns
ns
5.0
4.0
1.0
1.0
5.5
4.0
tH
Hold Time, HIGH or LOW
3.3
−3.0
−1.5
4.0
Dn to LE
5.0
tW
LE Pulse Width,
HIGH
3.3
5.0
2.0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
TA = +25°C
TA = −40°C to +85°C
C
L = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 9)
Min
Typ
Max
Min Max
tPLH
Propagation Delay
5.0
5.0
5.0
5.0
2.5
8.5
8.0
8.5
8.0
10.0
1.5
1.5
2.0
1.5
11.5
11.5
11.5
11.5
ns
ns
ns
ns
Dn to On
tPHL
tPLH
tPHL
Propagation Delay
Dn to On
2.0
2.5
2.0
10.0
11.0
10.0
Propagation Delay
LE to On
Propagation Delay
LE to On
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
2.0
2.5
1.5
8.0
7.5
9.0
7.5
9.5
9.0
1.5
1.5
2.5
1.0
10.5
10.5
12.5
10.0
ns
ns
ns
ns
11.0
8.5
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
C
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 10)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to LE
5.0
0.8
2.5
3.5
ns
tH
Hold Time, HIGH or LOW
Dn to LE
5.0
5.0
0
0
1.0
8.0
ns
ns
tW
LE Pulse Width, HIGH
2.0
7.0
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
40.0
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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