74ACT374SCTR [FAIRCHILD]
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20;
| 型号： | 74ACT374SCTR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74AC374, 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
General Description
■ I and I reduced by 50%
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are com-
mon to all flip-flops.
CC
OZ
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24mA
■ See 273 for reset version
■ See 377 for clock enable version
■ See 373 for transparent latch version
■ See 574 for broadside pinout version
■ See 564 for broadside pinout version with inverted
outputs
■ ACT374 has TTL-compatible inputs
Ordering Information
Order
Number
Package
Number
Package Description
74AC374SC
74AC374SJ
74AC374MTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC374PC
N20A
M20B
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT374SC
74ACT374SJ
74ACT374MSA
74ACT374MTC
M20D
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin
Names
Description
D –D
Data Inputs
0
7
CP
OE
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
O –O
0
7
Truth Table
Functional Description
Inputs
Outputs
The AC/ACT374 consists of eight edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
D
CP
OE
L
O
n
n
H
H
L
L
L
Z
X
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
−0.5V to +7.0V
CC
IK
DC Input Diode Current
V = −0.5V
−20mA
+20mA
I
V = V + 0.5
I
CC
V
DC Input Voltage
−0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= −0.5V
−20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
−0.5V to V + 0.5V
O
CC
I
±50mA
±50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
−65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
AC
CC
2.0V to 6.0V
4.5V to 5.5V
ACT
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
−40°C to +85°C
A
∆V / ∆t
Minimum Input Edge Rate, AC Devices:
from 30% to 70% of V , V @ 3.3V, 4.5V, 5.5V
125mV/ns
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
4
DC Electrical Characteristics for AC
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
3.0
V
= 0.1V or
OUT
1.5
2.1
2.1
V
IH
V
– 0.1V
CC
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
– 0.1V
V
V
IL
OUT
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
V
= V or V ,
0.36
0.36
0.44
0.44
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(2)
I
Maximum Input
Leakage Current
5.5
5.5
V = V , GND
±0.1
±1.0
±2.5
µA
µA
IN
I
CC
I
Maximum 3-STATE
Leakage Current
V (OE) = V , V ;
±0.25
OZ
I
IL IH
V = V , GND;
I
CC
V
= V , GND
O
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65V Max.
= 3.85V Min.
75
mA
mA
µA
OLD
OLD
OHD
(3)
I
−75
40.0
OHD
(2)
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
5
DC Electrical Characteristics for ACT
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
4.5
V
= 0.1V or
OUT
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
IH
V
− 0.1V
CC
5.5
4.5
5.5
4.5
5.5
4.5
V
Maximum LOW
Level Input Voltage
V
V
= 0.1V or
− 0.1V
1.5
V
V
IL
OUT
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= −50µA
4.49
5.49
OH
OUT
V
= V or V ,
3.86
3.76
IN
IL
IH
I
= −24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(4)
I
I
= −24mA
OH
V
Maximum LOW
4.5
5.5
4.5
= 50µA
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
Level Output Voltage
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 24mA
OL
5.5
V
= V or V ,
0.36
0.44
IN
IL
IH
(4)
I
= 24mA
OL
I
Maximum Input
Leakage Current
5.5
5.5
V = V , GND
±0.1
±1.0
±2.5
µA
µA
IN
I
CC
I
Maximum 3-STATE
Leakage Current
V = V , V ;
±0.25
OZ
I
IL IH
V
= V , GND
O
CC
I
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V − 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OHD
(5)
Output Current
I
= 3.85V Min.
−75
40.0
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
6
AC Electrical Characteristics for AC
T = +25°C,
T = −40°C to +85°,
A
A
C = 50pF
C = 50pF
L
L
(6)
Symbol
Parameter
V
(V)
Min.
60
Typ. Max.
Min.
Max.
Units
CC
f
Maximum Clock Frequency
3.3
110
155
11.0
8.0
60
100
1.5
1.5
2.0
1.5
1.5
1.0
1.5
1.0
2.0
2.0
1.0
1.0
MHz
MAX
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
100
3.0
2.5
2.5
2.0
3.0
2.0
2.5
2.0
3.0
2.0
2.0
1.5
t
Propagation Delay,
13.5
9.5
15.5
10.5
14.0
10.0
13.0
9.5
ns
ns
ns
ns
ns
ns
PLH
PHL
PZH
CP to O
n
t
Propagation Delay,
CP to O
10.0
7.0
12.5
9.0
n
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
9.5
11.5
8.5
7.0
t
9.0
11.5
8.5
13.0
9.5
PZL
6.5
t
10.5
8.0
12.5
11.0
11.5
8.5
14.5
12.5
12.5
10.0
PHZ
t
8.0
PLZ
6.5
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for AC
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(7)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Setup Time, HIGH or LOW,
3.3
2.0
1.0
−1.0
0
5.5
6.0
4.5
1.0
1.5
6.0
4.5
ns
S
D to CP
n
5.0
3.3
5.0
3.3
5.0
4.0
1.0
1.5
5.5
4.0
t
Hold Time, HIGH or LOW,
ns
ns
H
D to CP
n
t
CP Pulse Width, HIGH or LOW
4.0
2.5
W
Note:
7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
7
AC Electrical Characteristics for ACT
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(8)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
f
Maximum Clock
Frequency
5.0
100
2.0
2.0
160
8.5
8.0
90
2.0
1.5
MHz
MAX
t
Propagation Delay,
5.0
5.0
10.0
9.5
11.5
11.0
ns
ns
PLH
PHL
PZH
CP to O
n
t
Propagation Delay,
CP to O
n
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
1.5
1.5
1.5
8.0
8.0
8.5
7.0
9.5
9.0
1.5
1.5
1.0
1.0
10.5
10.5
12.5
10.0
ns
ns
ns
ns
t
PZL
PHZ
t
11.5
8.5
t
PLZ
Note:
8. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for ACT
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(9)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Setup Time, HIGH or LOW,
5.0
1.0
5.5
5.5
1.5
5.0
ns
S
D to CP
n
t
Hold Time, HIGH or LOW,
5.0
5.0
0
1.5
5.0
ns
ns
H
D to CP
n
t
CP Pulse Width,
HIGH or LOW
2.5
W
Note:
9. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Conditions
Typ.
Units
C
Input Capacitance
V
= OPEN
4.5
pF
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
8
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.65
0.51
0.35
1.27
PIN ONE
INDICATOR
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
11
Physical Dimensions (Continued)
26.92
24.89
PIN #1
7.11
6.09
3.43
3.17
5.33 MAX
(0.97)
1.78
7.87
7.62
7° TYP
1.14
7° TYP
3.55
2.54
0.36
3.17
0.38 MIN
10.92 MAX
0.56
0.20
0.35
.001[.025]
C
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
12
Physical Dimensions (Continued)
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
13
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™
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Global Power ResourceSM
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MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
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Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
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QS™
QT Optoelectronics™
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®
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®
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
14
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