74ACT646SPC [FAIRCHILD]
Octal Transceiver/Register with 3-STATE Outputs; 八路收发器/寄存器与3态输出
| 型号： | 74ACT646SPC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Transceiver/Register with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised October 2000
74AC646 • 74ACT646
Octal Transceiver/Register with 3-STATE Outputs
General Description
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data transfers
■ 3-STATE outputs
The AC/ACT646 consist of registered bus transceiver cir-
cuits, with outputs, D-type flip-flops and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental data handling
functions available are illustrated in Figures 1, 2, 3, and
Figure 4.
■ 300 mil dual-in-line package
■ Outputs source/sink 24 mA
■ ACT646 has TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC646SC
M24B
N24C
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74AC646SPC
74ACT646SC
74ACT646SPC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
A0–A7
B0–B7
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
CPAB, CPBA
SAB, SBA
G
Transmit/Receive Inputs
Output Enable Input
DIR
Direction Control Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010132
www.fairchildsemi.com
Function Table
Inputs
DIR CPAB CPBA SAB SBA
Data I/O (Note 1)
Function
A0–A7 B0–B7
G
H
H
H
L
X
X
X
H
H
H
H
L
H or L H or L
X
X
X
L
X
X
X
X
X
X
X
L
Isolation
X
Input
Input
Input Clock An Data into A Register
Clock Bn Data into B Register
X
X
X
X
X
X
X
An to Bn—Real Time (Transparent Mode)
L
L
Output Clock An Data into A Register
A Register to Bn (Stored Mode)
L
H or L
H
H
X
X
X
X
L
Clock An Data into A Register and Output to Bn
Bn to An —Real Time (Transparent Mode)
Input Clock Bn Data into B Register
B Register to An (Stored Mode)
L
X
X
X
X
L
L
L
Output
L
L
H or L
H
H
L
L
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
Real Time Transfer
B-Bus to A-Bus
FIGURE 1.
FIGURE 2.
Storage from
Transfer from
Bus to Register
Register to Bus
FIGURE 3.
FIGURE 4.
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
V
IN = VIL or VIH
IOH = −12 mA
OH = −24 mA
IOH = −24 mA (Note 3)
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
V
V
I
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
IOUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
3.0
4.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
75
IOH = 12 mA
V
IOL = 24 mA
IOH = 24 mA (Note 3)
VI = VCC, GND
IIN (Note 5) Maximum Input Leakage Current
µA
mA
mA
µA
IOLD
IOHD
Minimum Dynamic
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 4)
−75
ICC (Note 5) Maximum Quiescent Supply Current
8.0
80.0
IOZT
Maximum I/O
VI (OE) = VIL, VIH
VI = VCC, GND
Leakage Current
5.5
±0.6
±6.0
µA
V
O = VCC, GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
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4
DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
1.5
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
VIN = VIL or VIH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
IOH= −24 mA
I
I
OH= −24 mA (Note 6)
OUT = 50 µA
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
0.1
0.1
VIN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
IOL= 24 mA
IOL = 24 mA (Note 6)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
± 0.1
± 1.0
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
0.6
1.5
mA
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
Maximum I/O
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
−75
V
5.5
8.0
80.0
µA
or GND
IOZT
VI (OE) = VIL, VIH
VI = VCC, GND
Leakage Current
5.5
±0.6
±6.0
µA
VO = VCC, GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
5
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AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Min
4.0
2.5
3.0
2.0
2.5
1.5
1.5
1.5
2.0
1.5
Typ
10.5
7.5
9.5
6.5
7.5
5.0
7.5
5.0
8.5
6.0
Max
16.5
12.0
14.5
10.5
12.0
8.0
Min
tPLH
Propagation Delay
3.0
2.0
2.5
1.5
2.0
1.0
1.5
1.0
1.5
1.5
18.5
13.0
16.0
11.5
13.5
9.0
ns
ns
ns
ns
Clock to Bus
5.0
tPHL
tPLH
tPHL
tPLH
Propagation Delay
Clock to Bus
3.3
5.0
Propagation Delay
Bus to Bus
3.3
5.0
Propagation Delay
Bus to Bus
3.3
12.5
9.0
13.5
9.5
5.0
Propagation Delay
SBA or SAB to An or Bn
(w/ An or Bn HIGH or LOW)
Propagation Delay
SBA or SAB to An or Bn
(w/ An or Bn HIGH or LOW)
Enable Time
3.3
13.5
10.0
15.5
11.0
5.0
ns
ns
tPHL
3.3
5.0
1.5
1.5
8.5
6.0
13.5
10.0
1.5
1.5
15.0
11.0
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.5
1.5
2.5
1.5
3.0
2.0
2.0
1.5
2.0
1.5
2.5
1.5
2.5
1.5
1.5
1.5
7.0
5.0
7.5
5.5
8.0
6.5
7.5
6.0
6.5
5.0
7.0
5.0
7.5
5.5
7.5
5.5
11.5
8.5
2.0
1.5
2.0
1.5
2.5
2.0
2.0
1.5
1.5
1.0
2.0
1.0
1.5
1.5
1.5
1.5
12.5
9.0
ns
ns
ns
ns
ns
ns
ns
ns
G to An or Bn
Enable Time
12.5
9.0
14.0
10.0
13.5
11.0
13.5
10.5
12.0
8.5
G to An or Bn
Disable Time
12.5
10.0
12.0
9.5
G to An or Bn
Disable Time
G to An or Bn
Enable Time
11.0
7.5
DIR to An or Bn
Enable Time
11.5
8.0
13.0
9.0
DIR to An or Bn
Disable Time
11.5
9.5
12.5
10.0
13.5
10.5
DIR to An or Bn
Disable Time
12.0
9.5
DIR to An or Bn
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 9)
3.3
Typ
2.0
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Bus to Clock
5.0
5.5
4.5
0
ns
ns
ns
5.0
1.5
4.0
0
tH
Hold Time, HIGH or LOW
Bus to Clock
3.3
−1.5
−0.5
2.0
5.0
0.5
3.5
3.5
1.0
4.5
3.5
tW
Clock Pulse Width
HIGH or LOW
3.3
5.0
2.0
Note 9: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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6
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 10)
Min
Typ
Max
Min
tPLH
Propagation Delay
5.0
5.0
5.0
5.0
3.5
12.0
12.0
8.5
14.5
3.0
3.5
2.5
2.0
16.0
16.0
11.5
11.5
ns
ns
ns
ns
Clock to Bus
tPHL
tPLH
tPHL
tPLH
Propagation Delay
Clock to Bus
4.0
3.0
2.5
14.5
10.5
10.5
Propagation Delay
Bus to Bus
Propagation Delay
Bus to Bus
8.5
Propagation Delay
SBA or SAB to An to Bn
(w/An or Bn, HIGH or LOW)
Propagation Delay
SBA or SAB to An to Bn
(w/An or Bn, HIGH or LOW)
Enable Time
5.0
5.0
3.0
3.0
9.5
9.5
11.5
11.5
2.5
2.5
12.5
12.5
ns
ns
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.0
3.5
5.0
3.5
2.0
3.5
5.0
3.5
9.0
9.0
11.0
11.0
13.0
12.5
10.5
10.5
12.5
12.5
1.5
3.0
4.5
3.0
1.5
3.0
4.5
3.0
12.0
12.0
14.5
14.0
11.5
11.5
13.5
13.5
ns
ns
ns
ns
ns
ns
ns
ns
G to An or Bn
Enable Time
G to An or Bn
Disable Time
10.5
10.0
6.5
G to An or Bn
Disable Time
G to An or Bn
Enable Time
DIR to An or Bn
Enable Time
6.5
DIR to An or Bn
Disable Time
8.5
DIR to An or Bn
Disable Time
8.5
DIR to An or Bn
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 11)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
BUS to Clock
5.0
2.5
7.0
8.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
Bus to Clock
5.0
5.0
0
2.5
7.0
2.5
8.0
tW
Clock Pulse Width
HIGH or LOW
4.5
Note 11: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
pF
Conditions
CIN
Input Capacitance
4.5
V
V
V
CC = OPEN
CC = 5.0V
CC = 5.0V
CI/O
CPD
Input/Output Capacitance
Power Dissipation Capacitance
15.0
60.0
pF
pF
7
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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