74ACTQ04SC [FAIRCHILD]

Quiet Series⑩ Hex Inverter; 安静Series⑩六反相器


型号：	74ACTQ04SC
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Quiet Series⑩ Hex Inverter 安静Series⑩六反相器栅极触发器逻辑集成电路光电二极管 PC
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August 1990

Revised November 1999

74ACTQ04

Quiet Series Hex Inverter

General Description

Features

The ACTQ04 contains six inverters and utilizes Fairchild

Quiet Series technology to guarantee quiet output switch-

ing and improved dynamic threshold performance. FACT

Quiet Series features GTO output control and under-

shoot corrector in addition to a split ground bus for superior

ACMOS performance.

■ I_CCreduced by 50%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Improved latch-up immunity

■ Outputs source/sink 24 mA

■ Has TTL-compatible inputs

Ordering Code:

Order Number Package Number

Package Description

74ACTQ04SC

74ACTQ04SJ

74ACTQ04PC

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

Description

Inputs

Outputs

A_n

O_n

FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.

DS010890

www.fairchildsemi.com

Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

Supply Voltage (V_CC

)

−0.5V to +7.0V

DC Input Diode Current (I_IK

V_I= −0.5V

)

Supply Voltage (V_CC

)

4.5V to 5.5V

0V to V_CC

−20 mA

+20 mA

Input Voltage (V_I)

V_I= V_CC+ 0.5V

Output Voltage (V_O)

0V to V_CC

DC Input Voltage (V_I)

−0.5V to V_CC+ 0.5V

Operating Temperature (T_A)

−40°C to +85°C

125 mV/ns

DC Output Diode Current (I_OK

)

Minimum Input Edge Rate (∆V/∆t)

_O= −0.5V

−20 mA

+20 mA

_INfrom 0.8V to 2.0V

_O= V_CC+ 0.5V

V_CC@ 4.5V, 5.5V

DC Output Voltage (V_O)

DC Output Source

−0.5V to V_CC+ 0.5V

or Sink Current (I_O)

±50 mA

DC V_CCor Ground Current

per Output Pin (I_CCor I_GND

)

± 50 mA

Note 1: Absolute maximum ratings are those values beyond which dam-

age to the device may occur. The databook specifications should be met,

without exception, to ensure that the system design is reliable over its

power supply, temperature, and output/input loading variables. Fairchild

does not recommend operation outside of databook specifications.

Storage Temperature (T_STG

DC Latch-up Source

or Sink Current

)

−65°C to +150°C

± 300 mA

140°C

Junction Temperature (T_J)

PDIP

DC Electrical Characteristics for ACTQ

V_CC

_A= +25°C

T_A= −40°C to +85°C

Symbol

Parameter

Units

Conditions

(V)

4.5

5.5

4.5

5.5

4.5

5.5

Typ

1.5

Guaranteed Limits

V_IH

Minimum HIGH Level

2.0

0.8

4.4

5.4

2.0

0.8

4.4

5.4

_OUT= 0.1V

or V_CC− 0.1V

_OUT= 0.1V

or V_CC− 0.1V

Input Voltage

1.5

V_IL

Maximum LOW Level

Input Voltage

1.5

V_OH

Minimum HIGH Level

Output Voltage

4.49

5.49

_OUT= −50 µA

_IN= V_ILor V_IH

4.5

5.5

4.5

5.5

3.86

4.86

0.1

3.76

4.76

0.1

I_OH= −24 mA

_OH= −24 mA (Note 2)

_OUT= 50 µA

V_OL

Maximum LOW Level

Output Voltage

0.001

0.1

_IN= V_ILor V_IH

4.5

5.5

5.0

0.36

± 0.1

0.44

± 1.0

1.5

I_OL= 24 mA

I_OL= 24 mA (Note 2)

V_I= V_CC, GND

V_I= V_CC− 2.1V

I_IN

Maximum Input Leakage Current

Maximum I_CC/Input

µA

I_CCT

I_OLD

I_OHD

I_CC

0.6

Minimum Dynamic

_OLD= 1.65V Max

_OHD= 3.85V Min

_IN= V_CCor GND

Output Current (Note 3)

−75

20.0

Maximum Quiescent Supply Current

Quiet Output Maximum Dynamic V_OL

2.0

1.5

V_OLP

1.1

Figure 1, Figure 2

(Note 4)(Note 5)

Figure 1, Figure 2

(Note 4)(Note 5)

(Note 4)(Note 6)

V_OLV

Quiet Output Minimum Dynamic V_OL

5.0

−0.6

−1.2

V_IHD

V_ILD

Minimum HIGH Level Dynamic Input Voltage

Maximum LOW LevelDynamic Input Voltage

5.0

1.9

1.2

2.2

0.8

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: DIP package.

Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.

Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V Input-under-test switching: 3V to threshold (V _ILD),

0V to threshold (V_IHD), f = 1 MHz.

www.fairchildsemi.com

AC Electrical Characteristics

V_CC

_A= +25°C

_A= −40°C to +85°C

_L= 50 pF

Max

_L= 50 pF

Symbol

Parameter

(V)

Units

(Note 7)

Min

Typ

Max

Min

t_PLH

Propagation Delay

5.0

2.0

6.5

0.5

7.5

2.0

8.0

1.0

Data to Output

Propagation Delay

Data to Output

Output to Output

Skew (Note 8)

t_PHL

2.0

7.5

1.0

t_OSHL

t_OSLH

Note 7: Voltage Range 5.0 is 5.0V ± 0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH to LOW (t_OSHL) or LOW to HIGH (t_OSLH). Parameter guaranteed by design.

Capacitance

Symbol

Parameter

Input Capacitance

Power Dissipation Capacitance

Typ

Units

Conditions

C_IN

4.5

_CC= OPEN

_CC= 5.0V

C_PD

www.fairchildsemi.com

V_OLP/V_OLVand V_OHP/V _OHV

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical

to the accuracy and repeatability of the tests. The following

is a brief description of the setup used to measure the

•

Determine the quiet output pin that demonstrates the

greatest noise levels. The worst case pin will usually be

the furthest from the ground pin. Monitor the output volt-

ages using a 50Ω coaxial cable plugged into a standard

SMB type connector on the test fixture. Do not use an

active FET probe.

noise characteristics of FACT

Equipment:

Hewlett Packard Model 8180A Word Generator

PC-163A Test Fixture

•

Measure V_OLPand V_OLVon the quiet output during the

worst case transition for active and enable. Measure

V_OHPand V_OHVon the quiet output during the worst

Tektronics Model 7854 Oscilloscope

Procedure:

case transition.for active and enable

1. Verify Test Fixture Loading: Standard Load 50 pF,

Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-

ability of the measurements.

500Ω.

2. Deskew the HFS generator so that no two channels

have greater than 150 ps skew between them. This

requires that the oscilloscope be deskewed first. It is

important to deskew the HFS generator channels

before testing. This will ensure that the outputs switch

simultaneously.

_ILDand V_IHD:

•

Monitor one of the switching outputs using a 50Ω coaxial

cable plugged into a standard SMB type connector on

the test fixture. Do not use an active FET probe.

•

First increase the input LOW voltage level, V_IL, until the

3. Terminate all inputs and outputs to ensure proper load-

ing of the outputs and that the input levels are at the

correct voltage.

output begins to oscillate or steps out a min of 2 ns.

Oscillation is defined as noise on the output LOW level

that exceeds V_ILlimits, or on output HIGH levels that

4. Set the HFS generator to toggle all but one output at a

frequency of 1 MHz. Greater frequencies will increase

DUT heating and effect the results of the measure-

ment.

exceed V_IHlimits. The input LOW voltage level at which

oscillation occurs is defined as V_ILD

Next decrease the input HIGH voltage level, V_IH, until

the output begins to oscillate or steps out a min of 2 ns.

Oscillation is defined as noise on the output LOW level

that exceeds V_ILlimits, or on output HIGH levels that

exceed V_IHlimits. The input HIGH voltage level at which

oscillation occurs is defined as V _IHD

Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-

ability of the measurements.

V_OHVand V_OLPare measured with respect to ground reference.

Input pulses have the following characteristics: f = 1 MHz, t_r= 3 ns, t_f

3 ns, skew < 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

5. Set the HFS generator input levels at 0V LOW and 3V

HIGH for ACT devices and 0V LOW and 5V HIGH for

AC devices. Verify levels with an oscilloscope.

FIGURE 2. Simultaneous Switching Test Circuit

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

Package Number M14A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

74ACTQ04SC [FAIRCHILD]

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