74ACTQ18825MTD [FAIRCHILD]
18-Bit Buffer/Line Driver with 3-STATE Outputs; 18位与3态输出缓冲器/线路驱动器
| 型号： | 74ACTQ18825MTD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 18-Bit Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1991
Revised January 2000
74ACTQ18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The ACTQ18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
■ Utilizes Fairchild FACT Quiet Series technology
■ Broadside pinout allows for easy board layout
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin output skew
■ Separate control logic for each byte
The ACTQ18825 utilizes Fairchild FACT Quiet Series
technology to guarantee quiet output switching and
improved dynamic threshold performance. FACT Quiet
Series features GTO output control and undershoot cor-
rector for superior performance.
■ Extra data width for wider address/data paths or buses
carrying parity
■ Outputs source/sink 24 mA
■ Additional specs for Multiple Output Switching
■ Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ18825SSC
74ACTQ18825MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I17
O0–O17
Inputs
Outputs
FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010955
www.fairchildsemi.com
Connection Diagram
Functional Description
The ACTQ18825 contains eighteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but indepen-
dently of the other. The control pins may be shorted
together to obtain full 18-bit operation. The 3-STATE out-
puts are controlled by an Output Enable (OEn) input for
each byte. When OEn is LOW, the outputs are in 2-state
mode. When OEn is HIGH, the outputs are in the high
impedance mode, but this does not interfere with entering
new data into the inputs.
Truth Table
Inputs
Outputs
Byte 1 (0:8) Byte 2 (8:17) I0–I8 I9–I17 O0–O8 O9–O17
OE1 OE2 OE3 OE4
L
H
X
L
L
X
H
L
L
L
L
L
H
X
X
L
H
L
H
Z
Z
L
H
L
L
L
H
X
X
X
L
H
Z
Z
Z
L
H
X
H
L
X
H
H
L
L
L
H
X
L
H
Z
L
H
L
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC +0.5V
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V∆t)
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
V
V
O = −0.5V
−20 mA
+20 mA
O = VCC +0.5V
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
±50 mA
VCC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Per Output Pin
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
±50 mA
−65°C to +150°C
4000V
Storage Temperature
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
Minimum HIGH
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
= 0.1V
IH
OUT
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or V −0.1V
CC
V
V
Maximum LOW
Input Voltage
1.5
V
= 0.1V
IL
OUT
1.5
or V −0.1V
CC
Minimum HIGH
Output Voltage
4.49
5.49
OH
I
= −50 µA
OUT
V
= V or V
IN
OH
OH
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
= −24 mA
= −24 mA (Note 2)
V
Maximum LOW
Output Voltage
0.001
0.001
OL
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
V
I
I
= 24 mA
= 24 mA (Note 2)
I
Maximum 3-STATE
V = V , V
OZ
I
IL
IH
5.5
±0.5
±5.0
µA
Leakage Current
V
= V , GND
O
CC
I
Maximum Input Leakage Current
5.5
5.5
5.5
5.5
± 0.1
± 1.0
1.5
µA
mA
µA
V = V , GND
I CC
IN
I
Maximum I /Input
CC
0.6
V = V −2.1V
CCT
I
CC
I
Maximum Quiescent Supply Current
Minimum Dynamic
8.0
80.0
75
V
V
V
= V or GND
CC
CC
IN
I
mA
mA
= 1.65V Max
= 3.85V Min
OLD
OLD
OHD
I
Output Current (Note 2)
Quiet Output
−75
OHD
V
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
OLP
OLV
OHP
OHV
5.0
0.5
0.8
V
Maximum Dynamic V
Quiet Output
OL
V
V
V
5.0
5.0
−0.5
−0.8
V
V
Minimum Dynamic V
OL
Maximum Overshoot
V
V
+ 1.0
V
V
+ 1.5
OH
OH
Minimum V
CC
5.0
− 1.0
− 1.8
V
OH
OH
V
Droop
CC
V
V
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.0
5.0
1.7
1.2
2.0
0.8
V
V
IHD
ILD
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
3
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AC Electrical Characteristics
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 8)
5.0
Units
L
Min
2.0
2.0
2.0
2.0
1.5
1.5
Typ
5.3
5.6
6.3
6.5
4.5
5.1
Max
8.4
8.7
9.6
9.7
7.3
8.5
Min
Max
t
t
t
t
t
t
Propagation Delay
2.0
2.0
2.0
2.0
1.5
1.5
9.0
9.2
PHL
ns
ns
ns
Data to Output
Output Enable
Time
PLH
PZL
PZH
PLZ
PHZ
5.0
5.0
10.3
10.4
7.6
Output Disable
Time
8.8
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
Extended AC Electrical Characteristics
T
= −40°C to +85°C
T = −40°C to +85°C
A
A
V
= Com
V
= Com
CC
CC
C
= 50 pF
C = 250 pF
L
L
Symbol
Parameter
Units
16 Outputs Switching
(Note 9)
Typ
8.0
(Note 10)
Min
6.5
5.5
6.1
6.5
3.1
3.5
Max
Min
Max
t
Propagation Delay
9.8
8.9
9.2
9.4
6.1
6.5
PLH
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
Data to Output
6.5
PHL
PZH
PZL
Output Enable Time
7.6
(Note 11)
(Note 12)
7.8
Output Disable Time
5.0
PHZ
PLZ
5.2
Pin to Pin Skew
OSHL
1.5
2.0
2.0
(Note 13)
HL Data to Output
Pin to Pin Skew
t
OSLH
(Note 13)
LH Data to Output
Pin to Pin Skew
t
OST
(Note 13)
LH/HL Data to Output
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 11: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 12: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
), LOW-to-HIGH (t
), or any combination switching LOW-to-HIGH and/or HIGH-
OSLH
OSHL
to-LOW (t
).
OST
Capacitance
Symbol
Parameter
Typ
4.5
95
Units
pF
Conditions
C
Input Pin Capacitance
V
V
= 5.0V
= 5.0V
IN
CC
CC
C
Power Dissipation Capacitance
pF
PD
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4
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
V
OLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case transition for active and enable
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD
:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
•
•
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 14: V
and V
are measured with respect to ground refer-
OHV
OLP
ence.
Note 15: Input pulses have the following characteristics: f
3 ns, t 3 ns, skew < 150 ps.
= 1 MHz,
t
=
=
f
r
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
5
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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