74ACTQ245MSAX [FAIRCHILD]
Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, MO-150, SSOP-20;
| 型号： | 74ACTQ245MSAX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, MO-150, SSOP-20 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74ACQ245, 74ACTQ245
Quiet Series™ Octal Bidirectional Transceiver with
3-STATE Inputs/Outputs
Features
General Description
■ I and I reduced by 50%
The ACQ/ACTQ245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for
bus-oriented applications. Current sinking capability is
24mA at both the A and B ports. The Transmit/Receive
(T/R) input determines the direction of data flow through
the bidirectional transceiver. Transmit (active-HIGH)
enables data from A Ports to B Ports; Receive (active-
LOW) enables data from B Ports to A Ports. The Output
Enable input, when HIGH, disables both A and B ports
by placing them in a HIGH Z condition.
CC
OZ
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24mA
■ Faster prop delays than the standard ACT245
The ACQ/ACTQ utilizes Fairchild Quiet Series™
technology to guarantee quiet output switching and
improve dynamic threshold performance. FACT Quiet
Series™ features GTO™ output control and undershoot
corrector in addition to a split ground bus for superior
performance.
Ordering Information
Package
Order Number
Number
Package Description
74ACQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74ACQ245SJ
M20D
M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ245SC
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74ACTQ245SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ245QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150"
Wide
74ACTQ245MSA
74ACTQ245MTC
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm
Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A –A
Side A 3-STATE Inputs or 3-STATE
Outputs
0
7
B –B
Side B 3-STATE Inputs or 3-STATE
Outputs
0
7
Truth Table
Inputs
OE
T/R
Outputs
L
L
H
L
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
–0.5V to +7.0V
CC
IK
DC Input Diode Current
V = –0.5V
–20mA
+20mA
I
V = V + 0.5V
I
CC
V
DC Input Voltage
–0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= –0.5V
–20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
–0.5V to V + 0.5V
O
CC
I
50mA
50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
–65°C to +150°C
300mA
DC Latch-Up Source or Sink Current
Junction Temperature
T
140°C
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
ACQ
CC
2.0V to 6.0V
4.5V to 5.5V
ACTQ
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
–40°C to +85°C
125mV/ns
A
∆V / ∆t
Minimum Input Edge Rate, ACQ Devices:
from 30% to 70% of V , V @ 3.0V, 4.5V, 5.5V
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACTQ Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
3
DC Electrical Characteristics for ACQ
T = +25°C T = –40°C to +85°C
A
A
Symbol
Parameter
Minimum HIGH Level
Input Voltage
V
(V)
Conditions
Typ.
1.5
Guaranteed Limits
Units
V
CC
3.0
V
V
V
= 0.1V or
2.1
2.1
IH
OUT
– 0.1V
CC
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
V
V
IL
OUT
– 0.1V
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
5.5
V
= V or V ,
0.36
0.36
0.1
0.44
0.44
1.0
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(3)
I
Maximum Input
Leakage Current
V = V , GND
µA
IN
I
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65V Max.
= 3.85V Min.
75
mA
mA
µA
OLD
OLD
(2)
I
–75
40.0
OHD
(3)
OHD
I
Maximum Quiescent
Supply Current
= V or GND
4.0
0.3
CC
IN
CC
I
Maximum I/O
5.5
V (OE) = V , V ;
3.0
µA
OZT
I
IL IH
Leakage Current
V = V , GND;
I
CC
V
= V , GND
O
CC
(4)
V
Quiet Output
Maximum Dynamic V
5.0
5.0
5.0
5.0
Figures 1 & 2
1.1
–0.6
3.1
1.5
–1.2
3.5
V
V
V
V
OLP
OL
(4)
V
Quiet Output Minimum
Dynamic V
Figures 1 & 2
OLV
OL
(5)
V
Minimum HIGH Level
Dynamic Input Voltage
IHD
5)
V
Maximum LOW Level
Dynamic Input Voltage
1.9
1.5
ILD
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
4. Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND.
5. Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (V ), 0V to threshold (V ), f = 1 MHz.
ILD
IHD
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
4
DC Electrical Characteristics for ACTQ
T = +25°C T = –40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
4.5
V
V
= 0.1V or
OUT
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
IH
– 0.1V
CC
5.5
4.5
5.5
4.5
5.5
4.5
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
1.5
V
V
IL
OUT
– 0.1V
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= –50µA
4.49
5.49
OH
OUT
V
= V or V ,
3.86
3.76
IN
IL
IH
I
= –24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(6)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
= 50µA
0.001 0.1
0.001 0.1
0.36
0.1
0.1
V
OL
OUT
V
= V or V ,
0.44
IN
IL
IH
I
= 24mA
OL
5.5
V
= V or V ,
0.36
0.44
IN
IL
IH
(6)
I
= 24mA
OL
I
Maximum Input Leakage
Current
5.5
5.5
V = V , GND
0.1
0.3
1.0
3.0
µA
µA
IN
I
CC
I
Maximum 3-STATE
Leakage Current
V = V , V ,
I IL IH
OZT
V
= V , GND
O
CC
I
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V – 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OHD
(7)
I
Output Current
= 3.85V Min.
–75
40.0
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
(8)
V
Quiet Output Maximum
5.0
5.0
5.0
5.0
Figures 1 & 2
1.1
1.5
V
V
V
V
OLP
Dynamic V
OL
(8)
V
Quiet Output Minimum
Dynamic V
Figures 1 & 2
–0.6 –1.2
OLV
OL
(9)
V
Minimum HIGH Level
Dynamic Input Voltage
1.9
1.2
2.2
0.8
IHD
(9)
V
Maximum LOW Level
Dynamic Input Voltage
ILD
Notes:
6. All outputs loaded; thresholds on input associated with output under test.
7. Maximum test duration 2.0ms, one output loaded at a time.
8. Max number of outputs defined as (n). n–1 Data Inputs are driven 0V to 3V; one output @ GND.
9. Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (V ), 0V to threshold (V ) f = 1 MHz.
ILD
IHD
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
5
AC Electrical Characteristics for ACQ
T = +25°C,
T = –40°C to +85°C,
A
A
C = 5 pF
C = 50pF
L
L
(10)
Symbol
Parameter
V
(V)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min.
2.0
1.5
3.0
2.0
1.0
1.0
Typ. Max.
Min.
Max.
10.5
7.0
Units
CC
t
, t
Propagation Delay,
Data to Output
7.5
5.0
8.5
6.0
8.5
7.5
1.0
0.5
10.0
6.5
2.0
1.5
3.0
2.0
1.0
1.0
ns
PHL PLH
t
t
, t
Output Enable Time
Output Disable Time
Output to Output Skew,
13.0
8.5
13.5
9.0
ns
ns
ns
PZL PZH
, t
14.5
9.5
15.0
10.0
1.5
PHZ PLZ
t
, t
1.5
OSHL OSLH
(11)
Data to Output
1.0
1.0
Notes:
10. Voltage range 5.0 is 5.0V 0.5V. Voltage range 3.3 is 3.3V 0.3V.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSHL
OSLH
AC Electrical Characteristics for ACTQ
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(12)
Symbol
Parameter
V
(V)
Min.
Typ. Max.
Min.
Max.
Units
CC
t
, t
Propagation Delay,
Data to Output
5.0
1.5
5.5
7.0
1.5
7.5
ns
PHL PLH
t
t
, t
Output Enable Time
Output Disable Time
Output to Output Skew,
5.0
5.0
5.0
2.0
1.0
7.0
8.0
0.5
9.0
10.0
1.0
2.0
1.0
9.5
10.5
1.0
ns
ns
ns
PZL PZH
, t
PHZ PLZ
t
, t
OSHL OSLH
(13)
Data to Output
Notes:
12. Voltage range 5.0 is 5.0V 0.5V
13. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSHL
OSLH
Capacitance
Symbol
Parameter
Conditions
Typ.
4.5
Units
pF
C
Input Capacitance
V
V
V
= OPEN
= 5.0V
= 5.0V
IN
I/O
PD
CC
CC
CC
C
C
Input/Output Capacitance
15
pF
Power Dissipation Capacitance
80.0
pF
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
6
FACT Noise Characteristics
The setup of a noise characteristics measurement is crit-
ical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to mea-
sure the noise characteristics of FACT.
V
/V
and V
/V
:
OLP OLV
OHP OHV
■ Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50Ω coaxial cable plugged into a
standard SMB type connector on the test fixture. Do
not use an active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
■ Measure V
and V
on the quiet output during
OLP
OLV
the worst case transition for active and enable.
Measure V and V on the quiet output during
the worst case active and enable transition.
Tektronics Model 7854 Oscilloscope
OHP
OHV
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
■ Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
and V
:
ILD
IHD
■ Monitor one of the switching outputs using a 50Ω
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are at
the correct voltage.
■ First increase the input LOW voltage level, V , until
IL
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
4. Set the HFS generator to toggle all but one output at
a frequency of 1 MHz. Greater frequencies will
increase DUT heating and effect the results of the
measurement.
level that exceeds V limits, or on output HIGH levels
IL
that exceed V limits. The input LOW voltage level at
IH
which oscillation occurs is defined as V
.
ILD
■ Next decrease the input HIGH voltage level, V , until
IH
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds V limits, or on output HIGH levels
IL
that exceed V limits. The input HIGH voltage level at
IH
which oscillation occurs is defined as V
.
IHD
■ Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Notes:
14. V
and V
are measured with respect to ground
OHV
OLP
reference.
15. Input pulses have the following characteristics:
f = 1MHz, t = 3ns, t = 3ns, skew < 150ps.
r
f
Figure 1. Quiet Output Noise Voltage Waveforms
Figure 2. Simultaneous Switching Test Circuit
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
7
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.65
0.51
0.35
1.27
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Figure 5. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
11
Physical Dimensions (Continued)
Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
12
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
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®
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Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
Power247®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
Ultra FRFET™
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VCX™
FAST®
OPTOPLANAR®
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®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1989 Fairchild Semiconductor Corporation
74ACQ245, 74ACTQ245 Rev. 1.5.1
www.fairchildsemi.com
13
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