74ACTQ374PCX [FAIRCHILD]
Quiet Series⑩ Octal D-Type Flip-Flop with 3-STATE Outputs; 静音系列™八路D型触发器带3态输出
| 型号： | 74ACTQ374PCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Series⑩ Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总11页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1989
Revised November 1999
74ACQ374 • 74ACTQ374
Quiet Series Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
Features
■ ICC and IOZ reduced by 50%
The ACQ/ACTQ374 is a high-speed, low-power octal D-
type flip-flop featuring separate D-type inputs for each flip-
flop and 3-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common
to all flip-flops.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
The ACQ/ACTQ374 utilizes FACT Quiet Series technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
■ Buffered positive edge-triggered clock
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard AC/ACT374
Ordering Code:
Order Number Package Number
Package Description
74ACQ374SC
74ACQ374SJ
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ374PC
74ACTQ374SC
74ACTQ374SJ
74ACTQ374QSC
74ACTQ374PC
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MQA20
N20A
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010238
www.fairchildsemi.com
Logic Symbols
Functional Description
The ACQ/ACTQ374 consists of eight edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D-type inputs that meet the setup
and hold time requirements on the LOW-to-HIGH Clock
(CP) transition. With the Output Enable (OE) LOW, the
contents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
IEEE/IEC
Truth Table
Inputs
CP
Outputs
Dn
H
L
OE
L
On
H
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
ACQ
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACTQ
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
ACTQ devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
−65°C to +150°C
±300 mA
Storage Temperature (TSTG
)
V
IN from 0.8V to 2.0V
DC Latch-Up Source or Sink Current
Junction Temperature (TJ)
PDIP
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
140°C
DC Electrical Characteristics for ACQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
2.1
V
OUT = 0.1V
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
V
IN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
5.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
0.36
0.36
0.36
±0.1
0.44
0.44
0.44
±1.0
75
I
I
I
OL = 12 mA
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current
µA
mA
mA
µA
VI = VCC, GND
IOLD
IOHD
Minimum Dynamic
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
40.0
ICC (Note 4) Maximum Quiescent Supply Current
4.0
±0.25
1.5
IOZ
Maximum 3-STATE
Leakage Current
VI (OE) = VIL, VIH
VI = VCC, GND
5.5
5.0
±2.5
µA
V
O = VCC, GND
VOLP
Quiet Output
1.1
V
Figure 1, Figure 2
(Note 5)(Note 6)
Maximum Dynamic VOL
3
www.fairchildsemi.com
DC Electrical Characteristics for ACQ (Continued)
VCC
T
A = +25°C
T
A = −40°C to +85°C
Guaranteed Limits
−1.2
Symbol
VOLV
Parameter
Quiet Output
Units
Conditions
(V)
Typ
5.0
−0.6
V
Figure 1, Figure 2
(Note 5)(Note 6)
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
VIHD
5.0
5.0
3.1
1.9
3.5
1.5
V
V
(Note 5)(Note 7)
(Note 5)(Note 7)
VILD
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
Note 5: DIP Package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
Input Voltage
1.5
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 8)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
I
I
OL = 24 mA
OL = 24 mA (Note 8)
I
IN (Note 4) Maximum Input Leakage Current
µA VI = VCC, GND
IOZ
Maximum 3-STATE
Current
VI = VIL, VIH
µA
5.5
5.5
±0.25
±2.5
V
O = VCC, GND
ICCT
Maximum
0.6
1.5
mA VI = VCC − 2.1V
ICC/Input (Note 4)
IOLD
Minimum Dynamic
5.5
5.5
75
mA
VOLD = 1.65V Max
IOHD
ICC
Output Current (Note 8)
Maximum Quiescent
Supply Current
−75
mA VOHD = 3.85V Min
VIN = VCC
5.5
5.0
5.0
4.0
1.5
40.0
µA
V
(Note 4)
VOLP
or GND
Quiet Output
Figure 1, Figure 2
(Note 10)(Note 11)
Figure 1, Figure 2
(Note 10)(Note 11)
(Note 10)(Note 12)
(Note 10)(Note 12)
1.1
Maximum Dynamic VOL
Quiet Output
VOLV
−0.6
−1.2
V
Minimum Dynamic VOL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
VIHD
VILD
5.0
5.0
1.9
1.2
2.2
0.8
V
V
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: DIP package.
Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND
Note 12: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
www.fairchildsemi.com
4
AC Electrical Characteristics for ACQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 13)
3.3
Units
Min
75
Typ
Max
Min
fMAX
Maximum Clock
70
85
MHz
ns
Frequency
5.0
90
tPLH
tPHL
tPZL
Propagation Delay
CP to On
3.3
3.0
2.0
3.0
2.0
1.0
1.0
9.5
6.5
9.5
6.5
9.5
8.0
1.0
0.5
13.0
8.5
3.0
2.0
3.0
2.0
1.0
1.0
13.5
9.0
5.0
Output Enable Time
3.3
13.0
8.5
13.5
9.0
ns
tPZH
tPHZ
tPLZ
5.0
Output Disable Time
3.3
14.5
9.5
15.0
10.0
1.5
ns
5.0
tOSHL
tOSLH
Output to Output Skew (Note 14)
CP to On
3.3
1.5
ns
5.0
1.0
1.0
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements for ACQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 15)
3.3
Units
Typ
0
tS
Setup Time, HIGH or LOW
Dn to CP
3.0
3.0
3.0
1.5
1.5
4.0
4.0
ns
ns
ns
5.0
0
3.0
1.5
1.5
4.0
4.0
tH
Hold Time, HIGH or LOW
Dn to CP
3.3
0
5.0
2.0
2.0
2.0
tW
CP Pulse Width,
HIGH or LOW
3.3
5.0
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
CL = 50 pF
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 16)
Min
Typ
Max
Min Max
fMAX
Maximum Clock
5.0
5.0
85
80
MHz
ns
Frequency
tPLH
Propagation Delay
CP to On
2.0
7.0
9.0
2.0
9.5
tPHL
tPZL tPZH
tPHZ tPLZ
tOSHL
Output Enable Time
Output Disable Time
Output to Output Skew (Note 17)
CP to On
5.0
5.0
2.0
1.0
7.5
8.0
9.0
2.0
1.0
9.5
ns
ns
10.0
10.5
5.0
0.5
1.0
1.0
ns
tOSLH
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
5
www.fairchildsemi.com
AC Operating Requirements for ACTQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 18)
Typ
Guaranteed Minimum
tS
tH
tH
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
0
3.0
1.5
4.0
3.0
ns
ns
ns
Hold Time, HIGH or LOW
0
1.5
4.0
Dn to CP
CP Pulse Width,
HIGH or LOW
2.0
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
42.0
www.fairchildsemi.com
6
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 19: VOHV and VOLP are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics: f = 1 MHz,
tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Package Number MQA20
www.fairchildsemi.com
10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11
www.fairchildsemi.com
相关型号：
©2020 ICPDF网 联系我们和版权申明