74ACTQ827SPC [FAIRCHILD]
Quiet Seriesa⑩ 10-Bit Buffer/Line Driver with 3-STATE Outputs; 安静Seriesa⑩ 10位缓冲器/线路与3态输出驱动器
| 型号： | 74ACTQ827SPC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Seriesa⑩ 10-Bit Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1990
Revised December 1998
74ACTQ827
Quiet Series 10-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
Features
■ Guaranteed simultaneous switching noise level and
The ACTQ827 10-bit bus buffer provides high performance
bus interface buffering for wide data/address paths or
buses carrying parity. The 10-bit buffers have NOR output
enables for maximum control flexibility. The ACTQ827 uti-
lizes Fairchild Quiet Series technology to guarantee quiet
output switching and improved dynamic threshold perfor-
mance. FACT Quiet Series features GTO output control
and undershoot corrector in addition to a split ground bus
for superior performance.
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ Functionally and pin-compatible to AMD’s AM29827
■ Has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ827SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
74ACTQ827SPC
N24C
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
IEEE/IEC
Pin Descriptions
Pin Names
OE1, OE2
Description
Output Enable
D0–D9
O0–O9
Data Inputs
Data Outputs
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010687.prf
www.fairchildsemi.com
Functional Description
Function Table
The ACTQ827 line driver is designed to be employed as
memory address driver, clock driver and bus-oriented
transmitter/receiver. The devices have 3-STATE outputs
controlled by the Output Enable (OE) pins. When the OE is
LOW, the device is transparent. When OE is HIGH, the
device is in 3-STATE mode.
Inputs
Outputs
Function
OE Dn
On
L
L
H
L
H
L
Transparent
Transparent
High Z
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Junction Temperature (TJ)
PDIP
Absolute Maximum Ratings(Note 1)
140°C
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Recommended Operating
Conditions
−20 mA
+20 mA
VI = VCC + 0.5V
Supply Voltage (VCC
Input Voltage (VI)
)
4.5V to 5.5V
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
DC Output Diode Current (IOK
)
Output Voltage (VO)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
VCC @ 4.5V, 5.5V
or Sink Current (IO)
± 50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
DC Latch-Up Source
or Sink Current
)
−65°C to +150°C
± 300 mA
DC Electrical Characteristic
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
V
= 0.1V
IH
OUT
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
Maximum LOW Level
Input Voltage
V
V
V
= 0.1V
IL
OUT
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
I
= −50 µA
OH
OUT
V
= V or V
IN
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
I
= −24 mA
OH
OH
OUT
= −24 mA (Note 2)
V
Maximum LOW Level
Output Voltage
0.001
0.001
= 50 µA
OL
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
V
I
I
= 24 mA
= 24 mA (Note 2)
I
I
Maximum Input
Leakage Current
Maximum 3-STATE
Current
µA
µA
V = V , GND
I CC
IN
5.5
±0.5
±5.0
V = V , V
OZ
I
IL
IH
V
= V , GND
CC
O
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
µA
V = V − 2.1V
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
V
V
V
= 1.65V Max
OLD
OHD
−75
80.0
= 3.85V Min
8.0
1.6V
−1.3
2.0
= V
CC
IN
or GND
V
V
V
V
Quiet Output
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
V
V
V
V
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
OLP
OLV
IHD
ILD
Maximum Dynamic V
Quiet Output
OL
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
1.2
0.8
(Note 4)(Note 6)
3
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DC Electrical Characteristic (Continued)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (V ), 0V to threshold. (V ), f = 1 MHz.
ILD
IHD
AC Electrical Characteristics
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 7)
5.0
Units
L
Min
Typ
Max
Min
Max
t
t
t
t
t
t
Propagation Delay
2.5
5.6
8.0
2.5
9.0
ns
PHL
PLH
Data to Output
t
Output Enable Time
Output Disable Time
Output to Output
Skew (Note 8)
5.0
5.0
5.0
3.0
1.0
7.1
5.8
0.5
10.0
8.0
3.0
1.0
11.0
8.5
ns
ns
ns
PZL PZH
t
PHZ PLZ
1.5
1.5
OSHL
OSLH
Data to Output
Note 7: Voltage Range 5.0 is 5.0V ±0.5V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH to LOW (t
design. Not tested.
) or LOW to HIGH (t
). Parameter guaranteed by
OSHL
OSLH
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
82
Units
pF
Conditions
C
C
V
V
= OPEN
= 5.0V
IN
CC
pF
PD
CC
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4
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
V
OLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD
:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the word generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
•
•
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 9: V
and V
are measured with respect to ground reference.
OLP
OHV
Note 10: Input pulses have the following characteristics: f = 1 MHz,
t
= 3 ns, t = 3 ns, skew < 150 ps.
r
f
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
5
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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