74ACTQ841CW [FAIRCHILD]

Bus Driver, ACT Series, 1-Func, 10-Bit, True Output, CMOS, DIE;


型号：	74ACTQ841CW
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Bus Driver, ACT Series, 1-Func, 10-Bit, True Output, CMOS, DIE 驱动逻辑集成电路
文件：	总7页 (文件大小：64K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

March 1990

Revised November 1998

74ACTQ841

Quiet Series 10-Bit Transparent Latch

with 3-STATE Outputs

General Description

Features

■ Guaranteed simultaneous switching noise level and

The ACTQ841 bus interface latch is designed to eliminate

the extra packages required to buffer existing latches and

provide extra data width for wider address/data paths or

buses carrying parity. The 841 is a 10-bit transparent latch,

a 10-bit version of the 373. The ACTQ841 utilizes Fairchild

Quiet Series technology to guarantee quiet output switch-

ing and improved dynamic threshold performance. FACT

Quiet Series features GTO output control and undershoot

corrector in addition to a split ground bus for superior per-

formance.

dynamic threshold performance

■ Guaranteed pin-to-pin skew AC performance

■ Inputs and outputs on opposite sides of package allow

easy interface with microprocessors

■ Improved latch-up immunity

■ Outputs source/sink 24 mA

■ Has TTL-compatible inputs

Ordering Code:

Order Number Package Number

Package Description

74ACTQ841SC

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC, MS-100, 0.300” Wide

74ACTQ841SPC

N24C

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

Pin Assignment

for DIP and SOIC

Pin Descriptions

Pin Names

D₀–D₉

Description

Data Inputs

O₀–O₉

3-STATE Outputs

Output Enable

Latch Enable

FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

DS010688.prf

www.fairchildsemi.com

Functional Description

The ACTQ841 consists of ten D-type latches with 3-STATE

outputs. The flip-flops appear transparent to the data when

Latch Enable (LE) is HIGH. This allows asynchronous

operation, as the output transition follows the data in transi-

tion.

On the LE HIGH-to-LOW transition, the data that meets the

setup and hold time is latched. Data appears on the bus

when the Output Enable (OE) is LOW. When OE is HIGH

the bus output is in the high impedance state.

Function Table

Inputs

Internal

Output

Function

High Z

Latched

Transparent

Latched

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

NC = No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Junction Temperature (T_J)

PDIP

Absolute Maximum Ratings(Note 1)

140°C

Supply Voltage (V_CC

)

− 0.5V to + 7.0V

DC Input Diode Current (I_IK

V_I= − 0.5V

)

Recommended Operating

Conditions

− 20 mA

+ 20 mA

V_I= V_CC+ 0.5V

Supply Voltage (V_CC

Input Voltage (V_I)

)

4.5V to 5.5V

0V to V_CC

DC Input Voltage (V_I)

− 0.5V to V_CC+ 0.5V

DC Output Diode Current (I_OK

)

Output Voltage (V_O)

0V to V_CC

_O= − 0.5V

− 20 mA

+ 20 mA

Operating Temperature (T_A)

Minimum Input Edge Rate ∆V/∆t

V_INfrom 0.8V to 2.0V

− 40°C to + 85°C

125 mV/ns

_O= V_CC+ 0.5V

DC Output Voltage (V_O)

DC Output Source

− 0.5V to V_CC+ 0.5V

V_CC@ 4.5V, 5.5V

or Sink Current (I_O)

± 50 mA

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, temperature, and output/input loading variables. Fairchild does not

recommend operation of FACT circuits outside databook specifications.

DC V_CCor Ground Current

per Output Pin (I_CCor I_GND

)

± 50 mA

Storage Temperature (T_STG

DC Latch-Up Source

or Sink Current

)

− 65°C to + 150°C

± 300 mA

DC Electrical Characteristics

= +25°C

T = − 40°C to +85°C

Symbol

Parameter

Units

Conditions

(V)

4.5

5.5

4.5

5.5

4.5

5.5

Typ

1.5

Guaranteed Limits

Minimum High Level

Input Voltage

2.0

0.8

4.4

5.4

= 0.1V

OUT

1.5

2.0

0.8

4.4

5.4

or V − 0.1V

Maximum Low Level

Input Voltage

1.5

= 0.1V

OUT

1.5

or V − 0.1V

Minimum High Level

Output Voltage

4.49

5.49

= − 50 µA

OUT

= V or V

IL IH

4.5

5.5

4.5

5.5

3.86

4.86

0.1

3.76

4.76

0.1

= − 24 mA

OUT

= − 24 mA (Note 2)

Maximum Low Level

Output Voltage

0.001

= 50 µA

0.1

= V or V

IL IH

4.5

5.5

0.36

± 0.1

0.44

± 1.0

= − 24 mA

= − 24 mA (Note 2)

Maximum Input

µA

V = V , GND

I CC

Leakage Current

Maximum 3-STATE

Leakage Current

5.5

± 0.5

± 5.0

V = V , V

= V , GND

Maximum I /Input

5.5

0.6

1.5

µA

V = V − 2.1V

CCT

OLD

OHD

Minimum Dynamic

Output Current (Note 3)

Maximum Quiescent

Supply Current

= 1.65V Max

OLD

OHD

−75

80.0

= 3.85V Min

8.0

1.5

= V or GND

Quiet Output

5.0

1.1

−0.6

1.9

Figure 1, Figure 2

(Note 4)(Note 5)

Figure 1, Figure 2

(Note 4)(Note 5)

(Note 4)(Note 6)

OLP

OLV

IHD

ILD

Maximum Dynamic V

Quiet Output

−1.2

2.2

Minimum Dynamic V

Minimum High Level

Dynamic Input Voltage

Maximum Low Level

Dynamic Input Voltage

1.2

0.8

(Note 4)(Note 6)

Note 2: All outputs loaded; thresholds on input associated with output under test.

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DC Electrical Characteristics (Continued)

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: PDIP package.

Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.

Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:

3V to threshold (V ), 0V to threshold (V ), f = 1 MHz.

ILD

IHD

AC Electrical Characteristics

= +25°C

= 50 pF

T = −40°C to +85°C

C = 50 pF

Symbol

Parameter

(V)

(Note 7)

5.0

Units

Min

Typ

Max

Min

Max

Propagation Delay

to O

2.5

7.0

9.5

2.0

10.0

12.0

PLH

PHL

PLH

PHL

PZH

PZL

Propagation Delay

LE to O

5.0

2.5

7.0

8.5

9.5

Output Enable Time

11.0

OE to O

Output Disable Time

5.0

1.0

6.0

0.5

9.0

1.0

9.5

1.0

PHZ

PLZ

OE to O

Output to Output

OSLH

OSHL

Skew D to O (Note 8)

Note 7: Voltage Range 5.0 is 5.0V ± 0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.

The specification applies to any outputs switching in the same direction, either HIGH to LOW (t

design. Not tested.

) or LOW to HIGH (t

). Parameter guaranteed by

OSLH

OSHL

AC Operating Requirements

= + 25

T = − 40°C to + 85°C

= 50 pF °C

C = 50 pF

Symbol

Parameter

(V)

(Note 9)

5.0

Units

Typ

Guaranteed Minimum

Setup Time, HIGH or LOW

3.0

to LE

Hold Time, HIGH or LOW

to LE

5.0

1.5

4.0

1.5

4.0

LE Pulse Width, HIGH

Note 9: Voltage Range 5.0 is 5.0V ±0.5V.

Capacitance

Symbol

Parameter

Typ

4.5

Units

Conditions

Input Capacitance

= OPEN

= 5.0V

Power Dissipation Capacitance

85.0

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FACT Noise Characteristics

The setup of a noise characteristics measurement is critical

to the accuracy and repeatability of the tests. The following

is a brief description of the setup used to measure the

noise characteristics of FACT.

_OLP/V_OLVand V_OHP/V_OHV:

•

Determine the quiet output pin that demonstrates the

greatest noise levels. The worst case pin will usually be

the furthest from the ground pin. Monitor the output volt-

ages using a 50Ω coaxial cable plugged into a standard

SMB type connector on the test fixture. Do not use an

active FET probe.

Equipment:

Hewlett Packard Model 8180A Word Generator

PC-163A Test Fixture

•

Measure V_OLPand V_OLVon the quiet output during the

Tektronics Model 7854 Oscilloscope

Procedure:

worst case transition for active and enable. Measure

V_OHPand V_OHVon the quiet output during the worst

1. Verify Test Fixture Loading: Standard Load 50 pF,

case active and enable transition.

500Ω.

Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-

ability of the measurements.

2. Deskew the HFS generator so that no two channels

have greater than 150 ps skew between them. This

requires that the oscilloscope be deskewed first. It is

important to deskew the HFS generator channels

before testing. This will ensure that the outputs switch

simultaneously.

V_ILDand V_IHD

•

Monitor one of the switching outputs using a 50Ω coaxial

cable plugged into a standard SMB type connector on

the test fixture. Do not use an active FET probe.

3. Terminate all inputs and outputs to ensure proper load-

ing of the outputs and that the input levels are at the

correct voltage.

•

First increase the input LOW voltage level, V_IL, until the

output begins to oscillate or steps out of a min of 2 ns.

Oscillation is defined as noise on the output LOW level

that exceeds V_ILlimits, or on output HIGH levels that

4. Set the HFS generator to toggle all but one output at a

frequency of 1 MHz. Greater frequencies will increase

DUT heating and effect the results of the measure-

ment.

exceed V_IHlimits. The input LOW voltage level at which

oscillation occurs is defined as V_ILD

5. Set the HFS generator input levels at 0V LOW and 3V

HIGH for ACT devices and 0V LOW and 5V HIGH for

AC devices. Verify levels with an oscilloscope.

•

Next decrease the input HIGH voltage level, V_IH, until

the output begins to oscillate or steps out a min of 2 ns.

Oscillation is defined as noise on the output LOW level

that exceeds V_ILlimits, or on output HIGH levels that

exceed V_IHlimits. The input HIGH voltage level at which

oscillation occurs is defined as V_IHD

Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-

ability of the measurements.

Note A: V

and V

are measured with respect to ground reference.

OHV

OLP

Note B: Input pulses have the following characteristics: f = 1 MHz, t = 3 ns,

= 3 ns, skew < 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

FIGURE 2. Simultaneous Switching Test Circuit

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M24B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide

Package Number N24C

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74ACTQ841CW [FAIRCHILD]

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