74ALVCH162373T [FAIRCHILD]
Low Voltage 16-Bit Transparent Latch with Bushold and 26з Series Resistors in Outputs; 低电压16位透明锁存器与Bushold和26ヘ串联电阻的输出
| 型号： | 74ALVCH162373T |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Transparent Latch with Bushold and 26з Series Resistors in Outputs |
| 文件： | 总6页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2001
Revised November 2001
74ALVCH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26Ω Series Resistors in Outputs
General Description
Features
■ 1.65V to 3.6V VCC supply operation
The ALVCH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ 26Ω series resistors in outputs
■ tPD (In to On)
3.8 ns max for 3.0V to 3.6V VCC
5.0 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
The ALVCH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The ALVCH162373 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model > 2000V
The 74ALVCH162373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
Machine model > 200V
The 74ALVCH162373 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Ordering Code:
Ordering Number Package Number
Package Description
74ALVCH162373T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
LEn
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
I0–I15
O0–O15
Outputs
© 2001 Fairchild Semiconductor Corporation
DS500708
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Connection Diagram
Truth Tables
Inputs
OE1
Outputs
O0–O7
LE1
I0–I7
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
Inputs
OE2
Outputs
O8–O15
LE2
I8–I15
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
H
L
= HIGH Voltage Level
= LOW Voltage Level
X
Z
O
= Immaterial (HIGH or LOW, control inputs may not float)
= High Impedance
0 = Previous O0 before HIGH-to-LOW of Latch Enable
Functional Description
The 74ALVCH162373 contains sixteen edge D-type
latches with 3-STATE outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The 3-
STATE outputs are controlled by the Output Enable (OEn)
input. When OEn is LOW the standard outputs are in the 2-
state mode. When OEn is HIGH, the standard outputs are
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
in the high impedance mode but this does not interfere with
entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 2)
−0.5V to VCC +0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
)
Input Voltage (VI)
VI < 0V
−50 mA
−50 mA
±50 mA
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
0V to VCC
DC Output Diode Current (IOK
O < 0V
DC Output Source/Sink Current
(IOH/IOL
)
−40°C to +85°C
V
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V.
Note 3: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.7
2.0
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x VCC
0.7
V
V
0.8
VOH
I
I
I
I
OH = −100 µA
OH = −2 mA
OH = −4 mA
OH = −6 mA
1.65 - 3.6 VCC - 0.2
1.65
2.3
1.2
1.9
1.7
2.4
2
2.3
3.0
I
I
I
I
I
I
OH = −8 mA
OH = −12 mA
OL = 100 µA
OL = 2 mA
2.7
3.0
2
VOL
LOW Level Output Voltage
1.65 - 3.6
1.65
2.3
0.2
0.45
0.4
OL = 4 mA
OL = 6 mA
2.3
0.55
0.55
0.6
V
3.0
I
I
OL = 8 mA
2.7
OL = 12 mA
3
0.8
II
Input Leakage Current
Bushold Input Minimum
Drive Hold Current
0 ≤ VI ≤ 3.6V
3.6
±5.0
µA
µA
II(HOLD)
VIN = 0.58V
VIN = 1.07V
VIN = 0.7V
VIN = 1.7V
VIN = 0.8V
VIN = 2.0V
1.65
1.65
2.3
25
−25
45
2.3
−45
75
3.0
3.0
−75
0 < VO ≤ 3.6V
0 ≤ VO ≤ 3.6V
3.6
±500
±10
40
IOZ
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
3.6
µA
µA
µA
ICC
VI = VCC or GND, IO = 0
IH = VCC − 0.6V
3.6
∆ICC
V
3 - 3.6
750
3
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AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
C
L = 50 pF
C
L = 30 pF
CC = 1.8V ± 0.15V
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
VCC = 2.7V
V
CC = 2.5V ± 0.2V
V
Min
Max
Min
Max
Min
Max
Min
Max
t
PHL, tPLH
Propagation Delay
1.3
3.8
1.5
1.5
5.0
1.0
4.5
1.5
9.0
ns
ns
Bus to Bus
tPHL, tPLH
Propagation Delay
LE to Bus
1.3
4.1
5.4
1.0
4.9
1.5
9.8
t
PZL, tPZH
Output Enable Time
Output Disable Time
Pulse Width
1.3
1.3
1.5
1.5
1.0
4.4
4.5
1.5
1.5
1.5
1.5
1.0
5.9
4.9
1.0
1.0
1.5
1.5
1.0
5.4
4.4
1.5
1.5
4.0
2.5
1.0
9.8
7.9
ns
ns
ns
ns
ns
tPLZ, tPHZ
tW
tS
Setup Time
tH
Hold Time
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
VCC
Typical
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
VI = 0V or VCC
VI = 0V or VCC
3.3
3.3
3.3
2.5
6
7
pF
pF
COUT
CPD
Outputs Enabled f = 10 MHz, CL = 50 pF
20
20
pF
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4
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
VOL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.3V
V
OH − 0.15V
V
OH − 0.15V
VL
6V
6V
VCC*2
VCC*2
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output HIGH Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
REC Waveforms
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
t
5
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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