74ALVCH162373ZQLR [TI]
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS; 16位透明D类锁存器具有三态输出
| 型号： | 74ALVCH162373ZQLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总15页 (文件大小：809K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES583A–JULY 2004–REVISED OCTOBER 2004
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
•
•
•
Member of the Texas Instruments Widebus™
Family
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
2
3
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
4
5
6
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
7
V
CC
V
CC
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION/ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH162373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. This device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
V
CC
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive provide
the capability to drive bus lines without need for
interface or pullup components. OE does not affect
internal operations of the latch. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVCH162373DL
SN74ALVCH162373LR
SN74ALVCH162373GR
SN74ALVCH162373KR
TOP-SIDE MARKING
Tube
SSOP - DL
ALVCH162373
Tape and reel
Tape and reel
Tape and reel
-40°C to 85°C
TSSOP - DGG
VFBGA - GQL
ALVCH162373
VH2373
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES583A–JULY 2004–REVISED OCTOBER 2004
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
XXX
GQL PACKAGE
(TOP VIEW)
XXX
TERMINAL ASSIGNMENTS(1)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1LE
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2LE
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
VCC
GND
GND
VCC
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
G
H
J
K
K
(1) NC - No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q0
Z
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
1
24
2OE
1OE
1LE
25
48
2LE
C1
1D
C1
1D
2
13
2Q1
1Q1
47
36
2D1
1D1
To Seven Other Channels
Pin numbers shown are for the DGG and DL packages.
To Seven Other Channels
2
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES583A–JULY 2004–REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
MAX
4.6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
4.6
V
VO
IIK
Output voltage range(2)(3)
-0.5 VCC + 0.5
V
Input clamp current
VI < 0
-50
-50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
DGG package
DL package
θJA
Package thermal impedance(4)
63
°C/W
GQL package
42
Tstg
Storage temperature range
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VCC
VIH
High-level input voltage
1.7
2
VCC
V
VCC
0
0.35 × VCC
VIL
VO
Low-level input voltage
Output voltage
0
0.7
0.8
VCC
-2
V
V
0
0
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-6
IOH
High-level output current
Low-level output current
mA
mA
-8
-12
2
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
6
IOL
8
12
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10 ns/V
85 °C
TA
-40
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES583A–JULY 2004–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1) MAX UNIT
IOH = -100 µA
IOH = -2 mA
IOH = -4 mA
VCC - 0.2
1.2
1.9
1.7
2.4
2
VOH
2.3 V
V
IOH = -6 mA
3 V
IOH = -8 mA
IOH = -12 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
2.7 V
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
VOL
2.3 V
0.55
0.55
0.6
V
IOL = 6 mA
3 V
IOL = 8 mA
2.7 V
IOL = 12 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.8
II
3.6 V
±5
µA
µA
1.65 V
1.65 V
2.3 V
25
-25
45
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
2.3 V
-45
75
VI = 0.8 V
3 V
VI = 2 V
3 V
-75
VI = 0 to 3.6 V(2)
VO = VCC or GND
VI = VCC or GND,
3.6 V
±500
±10
40
IOZ
3.6 V
µA
µA
µA
ICC
IO = 0
3.6 V
∆ICC
One input at VCC - 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
750
Control inputs
Data inputs
Outputs
3
6
7
Ci
VI = VCC or GND
3.3 V
3.3 V
pF
pF
Co
VO = VCC or GND
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX
MIN
3.3
1.1
1.1
MAX MIN MAX
MIN
3.3
1.1
1.1
MAX
tw
tsu
th
Pulse duration, LE high or low
Setup time, data before LE↓
Hold time, data after LE↓
3.3
1.1
1.1
3.3
1.1
1.1
ns
ns
ns
4
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES583A–JULY 2004–REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
MAX
6.3
6.6
7.2
6.5
1
MIN
1
MAX
MIN MAX MIN MAX
D
5.3
5.6
6.5
5.6
0.5
1
1
4.5
5
1.1
1
4
4.2
5
tpd
Q
ns
LE
OE
OE
1
1
ten
tdis
Q
Q
1
1
1.5
1.5
6
1
ns
ns
ns
1
1
5.5
0.5
1.4
4.5
0.5
tsk(o)
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
20
6
TYP
22
TYP
26
8
Outputs enabled
Cpd Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
pF
Outputs disabled
6.5
5
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES583A–JULY 2004–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
t
t
L
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V
V
V
2.7 V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
2.5 V ± 0.2 V
2.7 V
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
74ALVCH162373DLG4
74ALVCH162373GRE4
74ALVCH162373GRG4
74ALVCH162373LRG4
74ALVCH162373ZQLR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SSOP
TSSOP
TSSOP
SSOP
DL
48
48
48
48
56
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ALVCH162373
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGG
DGG
DL
2000
2000
1000
1000
Green (RoHS
& no Sb/Br)
-40 to 85
ALVCH162373
ALVCH162373
ALVCH162373
VH2373
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
BGA
ZQL
Green (RoHS
& no Sb/Br)
-40 to 85
MICROSTAR
JUNIOR
SN74ALVCH162373DL
SN74ALVCH162373GR
SN74ALVCH162373KR
ACTIVE
ACTIVE
SSOP
DL
48
48
56
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 85
-40 to 85
-40 to 85
ALVCH162373
ALVCH162373
VH2373
TSSOP
DGG
GQL
2000
Green (RoHS
& no Sb/Br)
OBSOLETE
BGA
TBD
MICROSTAR
JUNIOR
SN74ALVCH162373LR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH162373
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
74ALVCH162373ZQLR BGA MI
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
CROSTA
R JUNI
OR
SN74ALVCH162373GR TSSOP
DGG
DL
48
48
2000
1000
330.0
330.0
24.4
32.4
8.6
15.8
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
SN74ALVCH162373LR
SSOP
11.35 16.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
74ALVCH162373ZQLR BGA MICROSTAR
JUNIOR
ZQL
56
1000
336.6
336.6
28.6
SN74ALVCH162373GR
SN74ALVCH162373LR
TSSOP
SSOP
DGG
DL
48
48
2000
1000
367.0
367.0
367.0
367.0
45.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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