74F163A [FAIRCHILD]
Synchronous Presettable Binary Counter; 同步可预置二进制计数器
| 型号： | 74F163A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Synchronous Presettable Binary Counter |
| 文件： | 总11页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2007
74F161A, 74F163A
tm
Synchronous Presettable Binary Counter
Features
General Description
■ Synchronous counting and loading
■ High-speed synchronous expansion
■ Typical count frequency of 120MHz
The 74F161A and 74F163A are high-speed synchro-
nous modulo-16 binary counters. They are synchro-
nously presettable for application in programmable
dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming
synchronous multi-stage counters. The 74F161A has an
asynchronous Master-Reset input that overrides all other
inputs and forces the outputs LOW. The 74F163A has a
Synchronous Reset input that overrides counting and
parallel loading and allows the outputs to be simulta-
neously reset on the rising edge of the clock. The
74F161A and 74F163A are high-speed versions of the
74F161 and 74F163.
Ordering Information
Order
Number
Package
Number
Package Description
74F161ASC
74F161ASJ
74F161APC
74F163ASC
74F163ASJ
74F163APC
M16A
M16D
N16E
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagrams
74F161A
74F163A
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
Logic Symbols
74F161A
IEEE/IEC
74F163A
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
U.L.
Input I / I
IH IL
Pin Names
Description
HIGH / LOW
1.0 / 1.0
1.0 / 2.0
1.0 / 1.0
1.0 / 1.0
1.0 / 2.0
1.0 / 1.0
1.0 / 2.0
50 / 33.3
50 / 33.3
Output I / I
OH OL
CEP
Count Enable Parallel Input
Count Enable Trickle Input
20µA / -0.6mA
20µA / -1.2mA
20µA / -0.6 mA
20µA / -0.6 mA
20µA / -1.2 mA
20µA / -0.6 mA
20µA / -1.2mA
-1mA / 20mA
-1mA / 20mA
CET
CP
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
MR (74F161A)
SR (74F163A)
P –P
0
3
PE
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Q –Q
0
3
TC
Terminal Count Output
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
2
Logic Equations:
Count Enable = CEP • CET • PE
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven
in parallel through a clock buffer. Thus all changes of the
Q outputs (except due to Master Reset of the 74F161A)
occur as a result of, and synchronous with, the LOW-to-
HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of prece-
dence: asynchronous reset (74F161A), synchronous
reset (74F163A), parallel load, count-up and hold. Five
control inputs—Master Reset (MR, 74F161A), Synchro-
nous Reset (SR, 74F163A), Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET)—
determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel load-
ing and allows all outputs to go LOW on the next rising
edge of CP. A LOW signal on PE overrides counting and
TC = Q • Q • Q • Q • CET
0
1
2
3
Mode Select Table
Action on the Rising
(1)
SR
L
PE CET CEP
Clock Edge (
)
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)
H
Load (P →Q )
n
n
H
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
allows information on the Parallel Data (P ) inputs to be
n
Note:
1. For 74F163A only
loaded into the flip-flops on the next rising edge of CP.
With PE and MR ('F161A) or SR (74F163A) HIGH, CEP
and CET permit counting when both are HIGH. Con-
versely, a LOW signal on either CEP or CET inhibits
counting.
State Diagram
The 74F161A and 74F163A use D-type edge triggered
flip-flops and changing the SR, PE, CEP and CET inputs
when the CP is in either state does not cause errors, pro-
vided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement syn-
chronous multi-stage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Please refer to the 74F568 data sheet. The TC output is
subject to decoding spikes due to internal race condi-
tions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, counters or
registers.
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
3
Block Diagram
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
T
Storage Temperature
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
STG
T
Ambient Temperature Under Bias
Junction Temperature Under Bias
A
T
J
V
V
Pin Potential to Ground Pin
CC
CC
(2)
V
Input Voltage
Input Current
IN
IN
(2)
I
V
Voltage Applied to Output in HIGH State (with V = 0V)
O
CC
Standard Output
–0.5V to V
CC
3-STATE Output
–0.5V to +5.5V
Current Applied to Output in LOW State (Max.)
ESD Last Passing Voltage (Min.)
twice the rated I (mA)
OL
4000V
Note:
2. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
T
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
A
V
+4.5V to +5.5V
CC
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
5
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
Input LOW Voltage
V
Conditions
Min. Typ. Max. Units
CC
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
2.0
V
V
V
V
IH
V
0.8
IL
V
Input Clamp Diode Voltage
Min.
Min.
I
= –18mA
–1.2
CD
OH
IN
V
Output HIGH
Voltage
10% V
2.5
2.7
CC
5% V
CC
V
I
Output LOW
Voltage
10% V
Min.
I
= 20mA
= 2.7V
0.5
V
OL
CC
OL
Input HIGH Current
Max.
Max.
V
V
5.0
7.0
µA
µA
IH
IN
I
Input HIGH Current
Breakdown Test
= 7.0V
BVI
IN
I
Output HIGH Leakage
Current
Max.
0.0
V
I
= V
CC
50
µA
V
CEX
OUT
V
I
Input Leakage Test
= 1.9µA, All Other Pins
4.75
–60
ID
ID
Grounded
Output Leakage Circuit
Current
0.0
V
= 150mV, All Other Pins
3.75
µA
mA
OD
IOD
Grounded
I
Input LOW Current
Max.
V
V
V
= 0.5V (CEP, CP, MR, P –P )
–0.6
–1.2
–150
IL
IN
IN
0
3
= 0.5V (CET, PE, SR)
= 0.0V
I
Output Short-Circuit
Current
Max.
Max.
mA
mA
OS
OUT
I
Power Supply Voltage
37
55
CC
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
6
AC Electrical Characteristics
T = +25°C,
T = –55°C to +125°C, T = 0°C to 70°C,
A A
A
V
= +5.0V,
V
= +5.0V,
V
= +5.0V,
CC
CC
CC
C = 50pF
C = 50pF
C = 50pF
L
L
L
Symbol
Parameter
Maximum Count Frequency
Propagation Delay,
Min. Typ. Max.
Min.
Max.
Min.
Max. Units
f
100
MHz
ns
MAX
t
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
5.5
5.5
7.5
6.0
6.0
7.5
10.0
8.5
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
5.5
9.0
11.5
10.0
10.0
16.5
15.5
9.0
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
5.5
8.5
11.0
9.5
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
CP to Q (PE Input HIGH)
n
t
t
t
t
t
t
t
t
Propagation Delay,
ns
ns
ns
CP to Q (PE Input LOW)
n
8.5
9.5
Propagation Delay,
CP to TC
10.0 14.0
10.0 14.0
15.0
15.0
8.5
Propagation Delay,
CET to TC
4.5
4.5
9.0
7.5
7.5
9.0
8.5
Propagation Delay,
12.0
14.0
13.0
ns
ns
MR to Q (74F161A)
n
t
Propagation Delay,
4.5
8.0
10.5
4.5
12.5
4.5
11.5
PHL
MR to TC (74F161A)
AC Operating Requirements
T = +25°C,
CC
T = –55°C to +125°C, T = 0°C to 70°C,
A A
A
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
CC
Symbol
t (H)
Parameter
Min.
5.0
5.0
2.0
2.0
11.0
8.5
2.0
0
Max.
Min.
5.5
5.5
2.5
2.5
13.5
10.5
3.6
0
Max.
Min.
5.0
5.0
2.0
2.0
11.5
9.5
2.0
0
Max.
Units
Setup Time, HIGH or LOW,
ns
S
P to CP
n
t (L)
S
t (H)
Hold Time, HIGH or LOW,
ns
ns
ns
ns
ns
ns
ns
H
P to CP
n
t (L)
H
t (H)
Setup Time, HIGH or LOW,
PE or SR to CP
S
t (L)
S
t (H)
Hold Time, HIGH or LOW,
PE or SR to CP
H
t (L)
H
t (H)
Setup Time, HIGH or LOW,
CEP or CET to CP
11.0
5.0
0
13.0
6.0
0
11.5
5.0
0
S
t (L)
S
t (H)
Hold Time, HIGH or LOW,
CEP or CET to CP
H
0
0
0
t (L)
H
t (H)
Clock Pulse Width (Load),
HIGH or LOW
5.0
5.0
4.0
6.0
5.0
5.0
5.0
5.0
8.0
5.0
5.0
5.0
4.0
7.0
5.0
W
t (L)
W
t (H)
Clock Pulse Width (Count),
HIGH or LOW
W
t (L)
W
t (L)
MR Pulse Width, LOW
(74F161A)
ns
ns
W
t
Recovery Time, MR to CP
(74F161A)
6.0
6.0
6.0
REC
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
7
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
10
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exhaustive list of all such trademarks.
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SPM®
STEALTH™
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SuperSOT¥-3
SuperSOT¥-6
SuperSOT¥-8
SyncFET™
Across the board. Around the world.¥
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ImpliedDisconnect¥
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CTL™
Current Transfer Logic™
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
11
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