74F163AD [NXP]
暂无描述;
| 型号： | 74F163AD |
| 厂家： | 
NXP |
| 描述： | 暂无描述 计数器 |
| 文件： | 总14页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counter
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification
IC15 Data Handbook
1996 Jan 29
Philips
Semiconductors
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
A Low level at the Master Reset (MR) input sets all the four outputs
of the flip-flops (Q0 – Q3) in 74F161A to Low levels, regardless of
the levels at CP, PE, CET and CEP inputs (thus providing an
asynchronous clear function). For the 74F163A, the clear function is
synchronous. A Low level at the Synchronous Reset (SR) input sets
all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next
positive-going transition on the clock (CP) input (provided that the
setup and hold time requirements for SR are met). This action
occurs regardless of the levels at PE, CET, and CEP inputs. The
synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters.
Both Count Enable (CEP and CET) inputs must be High to count.
The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
be used to enable the next cascaded stage (see Figure 2). The TC
output is subjected to decoding spikes due to internal race
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• Asynchronous Master Reset (74F161A)
• Synchronous Reset (74F163A)
• High speed synchronous expansion
• Typical count rate of 130MHz
• Industrial range (–40°C to +85°C) available
DESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be
used for high-speed counting. Synchronous operation is provided by
having all flip-flops clocked simultaneously on the positive-going
edge of the clock. The clock input is buffered.
conditions. Therefore, it is not recommended for use as clock or
asynchronous reset for flip-flops, registers, or counters.
The outputs of the counters may be preset to High or Low level. A
Low level at the Parallel Enable (PE) input disables the counting
action and causes the data at the D0–D3 inputs to be loaded into
the counter on the positive-going edge of the clock (provided that
the setup and hold requirements for PE are met). Preset takes place
regardless of the levels at Count Enable (CEP, CET) inputs.
TYPICAL
TYPICAL SUPPLY CURRENT
(TOTAL)
TYPE
f
MAX
74F161A
74F163A
130MHz
46mA
ORDERING INFORMATION
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
INDUSTRIAL RANGE
V
CC
V
CC
= 5V ±10%, T
= –40°C to +85°C
amb
amb
16-pin plastic DIP
16-pin plastic SO
N74F161AN, N74F163AN
N74F161AD, N74F163AD
I74F161AN, I74F163AN
SOT38-4
I74F161AD, I74F163AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D3
CEP
CET
CP
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
LOAD VALUE HIGH/LOW
20µA/0.6mA
Data inputs
Count Enable Parallel input
Count Enable Trickle input
Clock input (active rising edge)
Parallel Enable input (active Low)
1.0/1.0
20µA/0.6mA
1.0/2.0
20µA/1.2mA
1.0/1.0
20µA/0.6mA
PE
1.0/2.0
20µA/1.2mA
MR
Asynchronous Master Reset input
(active Low) for 74F161A
1.0/1.0
20µA/0.6mA
SR
Synchronous Reset input
(active Low) for 74F163A
1.0/1.0
20µA/0.6mA
TC
Terminal count output
Flip-flop outputs
50/33
50/33
1.0mA/20mA
1.0mA/20mA
Q0 – Q3
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
2
1996 Jan 29
853–0347 16300
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F161A PIN CONFIGURATION
74F163A PIN CONFIGURATION
SR
CP
D0
D1
D2
1
2
3
4
5
16
V
CC
MR
CP
D0
D1
D2
1
2
3
4
5
16
V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
D3
CEP
GND
6
7
8
D3
CEP
GND
6
7
8
9
PE
9
PE
SF00656
SF00657
74F161A LOGIC SYMBOL
74F163A LOGIC SYMBOL
3
4
5
6
3
4
5
6
D0
D1
D2
D3
D0
D1
D2
D3
9
7
9
7
PE
PE
CEP
CEP
10
2
CET
CP
TC
15
10
2
CET
CP
TC
15
1
MR
1
SR
Q2 Q3
12 11
Q2 Q3
12 11
Q0 Q1
Q0 Q1
V
= Pin 16
GND = Pin 8
V
= Pin 16
CC
GND = Pin 8
14
13
14
13
CC
SF00658
SF00659
74F161A LOGIC SYMBOL (IEEE/IEC)
74F163A LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16
CTR DIV 16
1
9
1
9
R
2R
M1
G3
G4
M1
G3
G4
7
7
10
2
10
2
C2 /1,3,4+
C2 /1,3,4+
3
4
5
6
14
13
12
11
3
4
5
6
14
13
12
11
1,2 D
1,2 D
15
15
4 CT=15
4 CT=15
SF00660
SF00661
3
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
STATE DIAGRAM
APPLICATIONS
+V
CC
0
1
2
3
4
5
6
7
8
D0 D1 D2 D3
PE
15
14
13
12
CEP
CET
CP
74F163A
TC
CLOCK
SR
Q0 Q1 Q2 Q3
SF00665
11
10
9
Figure 1. Maximum count modifying scheme
Terminal count = 6
SF00664
H H = Enable count
or
L L = Disable count
D0 D1 D2 D3
74F163A TC
D0 D1 D2 D3
74F163A TC
D0 D1 D2 D3
74F163A TC
D0 D1 D2 D3
74F163A TC
D0 D1 D2 D3
74F163A TC
PE
PE
PE
PE
PE
CEP
CET
CEP
CET
CEP
CET
CEP
CET
CEP
CET
CP
SR
CP
SR
CP
SR
CP
SR
CP
SR
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
CP
SF00666
Figure 2. Synchronous multistage counting scheme
74F161A MODE SELECT – FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
CEP
CET
PE
Dn
Qn
TC
L
X
X
X
X
X
L
L
Reset (clear)
Parallel load
Count
H
H
↑
↑
X
X
X
X
l
l
l
L
L
h
H
(1)
H
↑
h
h
h
X
count
(1)
H
H
X
X
l
X
l
h
h
X
X
q
q
(1)
L
n
Hold (do nothing)
X
n
4
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F163A MODE SELECT – FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SR
l
CP
↑
CEP
CET
PE
X
l
Dn
X
l
Qn
TC
L
X
X
X
h
l
X
X
X
h
X
l
L
L
Reset (clear)
Parallel load
Count
h
↑
L
h
↑
l
h
H
(2)
(2)
(2)
L
h
↑
h
h
h
X
X
X
count
h
X
X
q
q
n
n
Hold (do nothing)
h
X
H
h
L
l
=
=
=
=
=
=
=
=
=
High voltage level
High voltage level one setup prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup prior to the Low-to-High clock transition
Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
Don’t care
Low-to-High clock transition
The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)
The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)
q
n
X
↑
(1)
(2)
74F161A LOGIC DIAGRAM
2
CP
1
MR
9
PE
10
CET
7
CEP
3
D0
R
R
R
R
D
Q
Q
14
13
12
Q0
Q1
Q2
CP
4
D1
D
Q
Q
CP
5
D2
D
Q
Q
CP
6
D3
D
Q
Q
11
15
Q3
TC
CP
V
= Pin 16
CC
GND = Pin 8
SF00662
5
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F163A LOGIC DIAGRAM
2
CP
1
SR
9
PE
10
CET
7
CEP
3
D0
D
Q
Q
14
Q0
CP
4
D1
D
Q
Q
13
Q1
CP
5
D2
D
Q
Q
12
Q2
CP
6
D3
D
Q
Q
11
Q3
CP
15
TC
V
= Pin 16
CC
GND = Pin 8
SF00663
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
–0.5 to V
40
CC
I
mA
°C
°C
°C
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
amb
Operating free-air temperature range
Storage temperature range
T
stg
6
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
°C
IK
High-level output current
Low-level output current
OH
OL
20
Commercial range
Industrial range
0
+70
+85
T
amb
Operating free-air temperature range
–40
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
TYP
MAX
2.5
2.7
V
V
V
±10%V
±5%V
CC
V
V
= MIN, V = MAX,
IL
= MIN
CC
IH
V
High-level output voltage
I
= MAX
= MAX
OH
OH
3.4
0.30
0.30
–0.73
CC
0.50
±10%V
CC
V
V
= MIN, V = MAX,
IL
= MIN
CC
IH
V
V
Low-level output voltage
I
OL
OL
0.50
–1.2
100
20
V
±5%V
CC
Input clamp voltage
V
CC
V
CC
V
CC
= MIN, I = I
IK
V
IK
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
µA
µA
mA
mA
mA
mA
mA
I
I
= MAX, V = 2.7V
IH
I
CET, PE
Low-level input current
others
–1.2
–0.6
–150
55
I
I
I
V
CC
V
CC
V
CC
= MAX, V = 0.5V
IL
I
3
Short-circuit output current
= MAX
= MAX
-60
OS
CC
I
42
49
CCH
Supply current (total)
I
65
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
7
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
T
= –40°C to +85°C
amb
CC
amb
CC
amb
V
TEST
= +5.0V ± 10%
CC
SYMBOL
PARAMETER
UNIT
CONDITION
C = 50pF
L
C = 50pF
L
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN TYP MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
100
130
90
75
MHz
ns
max
t
t
Propagation delay
CP to Qn (PE = High)
2.0
4.0
4.0
6.5
6.5
10.0
2.0
4.0
7.0
11.0
2.0
4.0
7.0
11.0
PLH
PHL
t
t
Propagation delay
CP to Qn (PE = Low)
2.0
3.5
4.5
5.5
6.5
8.5
2.0
3.5
7.5
9.5
2.0
3.5
7.5
9.5
PLH
PHL
Waveform 1
Waveform 1
Waveform 2
Waveform 3
Waveform 3
ns
ns
ns
ns
ns
t
t
Propagation delay
CP to TC
5.0
4.5
7.5
7.5
10.5
10.5
5.0
4.0
11.5
11.5
5.0
4.0
11.5
11.5
PLH
PHL
t
t
Propagation delay
CET to TC
1.5
2.5
3.5
5.0
6.5
7.5
1.5
2.5
7.0
8.0
1.5
2.5
7.0
8.0
PLH
PHL
Propagation delay
MR to Qn
t
’F161A
’F161A
6.0
5.0
8.5
8.5
12.0
10.0
5.5
5.0
13.0
11.0
5.5
5.0
13.0
11.0
PHL
PHL
Propagation delay
MR to TC
t
AC SETUP REQUIREMENTS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
T
= –40°C to +85°C
amb
CC
amb
CC
amb
V
TEST
= +5.0V ± 10%
CC
SYMBOL
PARAMETER
UNIT
CONDITION
C = 50pF
L
C = 50pF
L
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MIN
MIN
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
5.0
5.0
5.0
5.0
5.0
5.0
s
Waveform 6
Waveform 6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
0
0
0
0
0
0
h
t (L)
h
t (H)
Setup time, High or Low
PE or SR to CP
Waveform
5 or 6
9.0
6.5
9.5
7.0
9.5
7.0
s
t (L)
s
t (H)
Hold time, High or Low
PE or SR to CP
Waveform
5 or 6
0
0
0
0
0
0
h
t (L)
h
t (H)
Setup time, High or Low
CET or CEP to CP
10.5
6.0
10.5
7.0
10.5
7.0
s
Waveform 4
Waveform 4
Waveform 1
Waveform 1
Waveform 3
Waveform 3
t (L)
s
t (H)
Hold time, High or Low
CET or CEP to CP
0
0
0
0
0
0
h
t (L)
h
t (H)
CP pulse width (Load)
High or Low
4.0
5.0
4.0
5.5
4.0
7.0
w
t (L)
w
t (H)
CP pulse width (Count)
High or Low
4.0
6.0
4.0
7.0
4.0
7.0
w
t (L)
w
MR pulse width
Low
t (L)
w
’F161A
’F161A
4.5
6.0
4.5
6.5
4.5
6.5
Recovery time
MR to CP
t
REC
8
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CP
V
V
V
CET
TC
V
V
M
M
M
M
M
t
(H)
t
(L)
t
PHL
w
w
t
t
PHL
PLH
t
PLH
V
M
V
V
V
M
Qn, TC
M
M
SF00667
SF00668
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Propagation Delay, CET Input to TC Output
t
w
(L)
V
MR
CP
V
M
M
CEP
V
V
V
V
M
t
M
M
M
REC
CET
t (H)
s
t (H)
h
t (L)
s
t (L)
h
V
M
t
CP
V
V
M
PHL
M
V
Qn, TC
M
SF00669
SF00670
Waveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Recovery Time
Waveform 4. CEP and CET Reset Setup and Hold Times
Dn
PE
CP
V
V
M
M
SR
CP
V
V
V
V
M
t
t
h
M
M
M
s
t (L)
t (L)
h
t (H)
t (H)
h
s
s
V
V
V
V
M
M
M
M
t (L)
t (L)
h
t (H)
t (H)
h
V
V
s
s
M
M
V
V
M
M
SF00671
SF00672
Waveform 5. Synchronous Reset Setup and Hold Times
Waveform 6. Parallel Data and Parallel Enable
Setup and Hold Times
9
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
74F
V
rep. rate
t
w
t
t
THL
amplitude
M
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
10
1996 Jan 29
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counters
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
11
1996 Jan 29
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counters
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
12
1996 Jan 29
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counters
NOTES
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
13
1996 Jan 29
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counter
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05084
Document order number:
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Philips
Semiconductors
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