74F169 [FAIRCHILD]
4-Stage Synchronous Bidirectional Counter; 4级同步双向计数器
| 型号： | 74F169 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4-Stage Synchronous Bidirectional Counter |
| 文件： | 总7页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised July 1999
74F169
4-Stage Synchronous Bidirectional Counter
General Description
Features
■ Asynchronous counting and loading
■ Built-in lookahead carry capability
■ Presettable for programmable operation
The 74F169 is
a
fully synchronous 4-stage up/down
counter. The 74F169 is a modulo-16 binary counter. Fea-
tures a preset capability for programmable operation, carry
lookahead for easy cascading and a U/D input to control
the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the LOW-to-
HIGH transition of the clock.
Ordering Code:
Order Number Package Number
Package Description
74F169SC
74F169SJ
74F169PC
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009488
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
CEP
CET
CP
P0–P3
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
PE
U/D
Q0–Q3
TC
Flip-Flop Outputs
50/33.3
50/33.3
−1 mA/20 mA
−1 mA/20 mA
Terminal Count Output (Active LOW)
Functional Description
Mode Select Table
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE is LOW,
the data on the P0–P3 inputs enters the flip-flops on the
Action on Rising
Clock Edge
PE CEP CET U/D
L
H
H
H
H
X
L
X
L
X
H
L
Load (Pn → Qn)
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
L
L
H
X
X
H
X
X
next rising edge of the clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH;
the U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input level.
Since the TC signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
State Diagram
1. Count Enable = CEP • CET • PE
2. Up: (74F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET
3. Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET
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2
Logic Diagram
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
0.8
IL
−1.2
Min
Min
I
I
I
= −18 mA
CD
OH
IN
10% V
5% V
2.5
2.7
= −1 mA
= −1 mA
CC
CC
CC
OH
OH
V
V
V
Output LOW
Voltage
10% V
OL
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
= 20 mA
= 2.7V
= 7.0V
OL
I
I
I
Input HIGH
IH
µA
µA
µA
V
V
V
V
IN
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
BVI
IN
CEX
= V
OUT
CC
V
I
= 1.9 µA
ID
ID
4.75
All Other Pins Grounded
V = 150 mV
IOD
I
I
Output Leakage
Circuit Current
OD
3.75
µA
0.0
All Other Pins Grounded
Input LOW Current
−0.6
−1.2
mA
Max
V
= 0.5V (except CET)
= 0.5V (CET)
IL
IN
V
V
V
IN
I
I
Output Short-Circuit Current
Power Supply Current
−60
−150
mA
mA
Max
Max
= 0V
OUT
OS
35
52
= LOW
O
CCL
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4
AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
Typ
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
90
Max
Min
60
Max
Min
70
Max
f
t
t
Maximum Count Frequency
Propagation Delay
MHz
ns
MAX
3.0
4.0
6.5
9.0
8.5
3.0
4.0
12.0
16.0
3.0
4.0
9.5
PLH
PHL
11.5
13.0
CP to Q (PE HIGH or LOW)
n
t
t
Propagation Delay
5.5
4.0
12.0
8.5
15.5
12.5
5.5
4.0
20.0
15.0
5.5
4.0
17.5
13.0
PLH
PHL
ns
ns
ns
CP to TC
t
t
Propagation Delay
2.5
2.5
4.5
8.5
6.5
2.5
2.5
9.0
2.5
2.5
7.0
PLH
PHL
11.0
12.0
12.0
CET to TC
t
t
Propagation Delay
3.5
4.0
8.5
8.0
11.5
12.0
3.5
4.0
16.0
14.0
3.5
4.0
12.5
13.0
PLH
PHL
U/D to TC
AC Operating Requirements
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
4.0
4.0
3.0
3.0
7.0
5.0
Max
Min
4.5
4.5
3.5
3.5
8.0
8.0
Max
Min
4.5
4.5
3.5
3.5
8.0
6.5
Max
t (H)
Setup Time, HIGH or LOW
S
t (L)
P to CP
n
S
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
to CP
H
H
P
n
t (H)
S
Setup Time, HIGH or LOW
CEP or CET to CP
t (L)
S
ns
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
CEP or CET to CP
0
0
0
H
H
0.5
1.0
0.5
t (H)
S
Setup Time, HIGH or LOW
8.0
8.0
10.0
10.0
9.0
9.0
t (L)
S
PE to CP
t
t
(H)
(L)
Hold Time, HIGH or LOW
1.0
0
1.0
0
1.0
0
H
H
PE to CP
t (H)
S
Setup Time, HIGH or LOW
11.0
7.0
14.0
12.0
12.5
8.5
t (L)
S
U/D to CP
ns
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
0
0
0
0
0
0
H
H
U/D to CP
t
t
(H)
(L)
CP Pulse Width
HIGH or LOW
4.0
7.0
6.0
9.0
4.5
8.0
W
W
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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