74F269 [FAIRCHILD]

8-Bit Bidirectional Binary Counter; 8位双向二进制计数器


型号：	74F269
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	8-Bit Bidirectional Binary Counter 8位双向二进制计数器计数器
文件：	总6页 (文件大小：71K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

April 1988

Revised September 2000

74F269

8-Bit Bidirectional Binary Counter

General Description

Features

■ Synchronous counting and loading

The 74F269 is

fully synchronous 8-stage up/down

counter featuring a preset capability for programmable

operation, carry lookahead for easy cascading and a U/D

input to control the direction of counting. All state changes,

whether in counting or parallel loading, are initiated by the

rising edge of the clock.

■ Built-in lookahead carry capability

■ Count frequency 100 MHz

■ Supply current 113 mA typ

■ 300 mil slimline package

Ordering Code:

Order Number Package Number

Package Description

74F269SC

M24B

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

74F269SPC

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Function Table

PE CEP CET U/D CP

Function

Parallel Load All

Flip-Flops

Hold

Hold (TC Held HIGH)

Count Up

Count Down

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= Transition LOW-to-HIGH

DS009510

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Unit Loading/Fan Out

Input I_IH/I_IL

U.L.

Pin Names

Description

Output I_OH/I_OL

HIGH/LOW

1.0/1.0

P₀–P₇

Parallel Data Inputs

20 µA/−0.6 mA

−1 mA/20 mA

Parallel Enable Input (Active LOW)

Up-Down Count Control Input

Count Enable Parallel Input (Active LOW)

Count Enable Trickle Input (Active LOW)

Clock Input

1.0/1.0

U/D

1.0/1.0

CEP

CET

1.0/1.0

Terminal Count Output (Active LOW)

Flip-Flop Outputs

5.0/33.3

50/33.3

Q₀–Q₇

Logic Diagram

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Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

Storage Temperature

−65°C to +150°C

Ambient Temperature under Bias

Junction Temperature under Bias

V_CCPin Potential to Ground Pin

Input Voltage (Note 2)

−55°C to +125°C

−55°C to +150°C

−0.5V to +7.0V

Free Air Ambient Temperature

Supply Voltage

0°C to +70°C

+4.5V to +5.5V

−0.5V to +7.0V

Input Current (Note 2)

−30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with V_CC= 0V)

Standard Output

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

−0.5V to V_CC

3-STATE Output

−0.5V to +5.5V

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Current Applied to Output

in LOW State (Max)

twice the rated I_OL(mA)

DC Electrical Characteristics

V_CC

Symbol

V_IH

Parameter

Input HIGH Voltage

Min

Typ

Max

Units

Conditions

2.0

Recognized as a HIGH Signal

Recognized as a LOW Signal

V_IL

Input LOW Voltage

Input Clamp Diode Voltage

Output HIGH

0.8

V_CD

V_OH

−1.2

Min

_IN= −18 mA

_OH= −1 mA

_OL= 20 mA

10% V_CC

5% V_CC

10% V_CC

2.5

2.7

Voltage

V_OL

I_IH

Output LOW Voltage

Input HIGH Current

Breakdown Test

Output HIGH

0.5

5.0

Min

µA

Max

_IN= 2.7V

I_BVI

7.0

µA

Max

0.0

_IN= 7.0V

I_CEX

_OUT= V_CC

Leakage Current

Input Leakage Test

V_ID

_ID= 1.9 µA,

All Other Pins Grounded

_IOD= 150 mV

All Other Pins Grounded

4.75

I_OD

Output Leakage

3.75

µA

0.0

Circuit Current

I_IL

Input LOW Current

Output Short-Circuit Current

Power Supply Current

−0.6

−150

125

Max

V_IN= 0.5V

V_OUT= 0V

V_O= HIGH

V_O= LOW

I_OS

I_CCH

I_CCL

−60

104

113

135

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AC Electrical Characteristics

_A= +25°C

_A= 0°C to +70°C

V_CC= 5.0V

_CC= +5.0V

Symbol

Parameter

Units

C_L= 50 pF

Min

100

3.5

4.5

3.5

4.5

3.5

3.0

4.5

5.0

3.5

4.5

3.5

4.0

Typ

Max

Min Max

f_MAX

Maximum Clock Frequency

3.5

4.5

3.5

4.5

3.5

3.0

4.5

3.5

4.5

3.5

4.0

MHz

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

Propagation Delay

CP to Q_n(Count-Up)

Propagation Delay

U/D to TC

8.0

10.5

7.5

7.0

11.0

10.0

11.0

10.5

11.5

10.5

11.0

10.0

7.0

7.5

Propagation Delay

CET to TC

7.0

10.5

10.0

10.5

7.0

Propagation Delay

CP to TC

Propagation Delay

CP to _Qn(Count-Down)

Propagation Delay

CP to Q_n(Load)

7.0

AC Operating Requirements

_A= +25°C

_CC= +5.0V

Max

_A= 0°C to +70°C

_CC= 5.0V

Min Max

Symbol

Parameter

Units

Min

3.5

3.0

1.0

5.5

t_S(H)

Setup Time, HIGH or LOW

Data to CP

4.0

3.0

2.0

1.0

6.5

t_S(L)

t_H(H)

t_H(L)

t_S(H)

t_S(L)

t_H(H)

t_H(L)

t_S(H)

t_S(L)

t_H(H)

t_H(L)

Hold Time, HIGH or LOW

Data to CP

Setup Time, HIGH or LOW

PE to CP

Hold Time, HIGH or LOW

PE to CP

Setup Time, HIGH or LOW

CET or CEP to CP

Hold Time, HIGH or LOW

CET or CEP to CP

6.0

8.0

6.5

9.0

_W(H)

_W(L)

Clock Pulse Width, HIGH or LOW

3.5

8.0

6.0

0.0

3.5

4.0

9.5

7.0

0.0

t_S(H)

t_S(L)

t_H(H)

t_H(L)

Setup Time, HIGH or LOW

U/D to CP

Hold Time, HIGH or LOW

U/D to CP

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Physical Dimensions inches (millimeters) unless otherwise noted

28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N24C

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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