74F537SC [FAIRCHILD]
1-of-10 Decoder with 3-STATE Outputs; 1 -10 -解码器与3态输出
| 型号： | 74F537SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 1-of-10 Decoder with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F537
1-of-10 Decoder with 3-STATE Outputs
Two input enables, active HIGH E2 and active LOW E1, are
General Description
available for demultiplexing data to the selected output in
either non-inverted or inverted form. Input codes greater
than BCD nine cause all outputs to go to the inactive state
(i.e., same polarity as the P input).
The 74F537 is one-of-ten decoder/demultiplexer with four
active HIGH BCD inputs and ten mutually exclusive out-
puts. A polarity control input determines whether the out-
puts are active LOW or active HIGH. The 74F537 has 3-
STATE outputs, and a HIGH signal on the Output Enable
(OE) input forces all outputs to the high impedance state.
Ordering Code:
Order Number Package Number
Package Description
74F537SC
74F537PC
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009550
www.fairchildsemi.com
Unit Loading/Fan Out
U.L.
Input IIH/IIL
Pin Names
Description
HIGH/LOW
Output IOH/IOL
A0–A3
E1
Address Inputs
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
Enable Input (Active LOW)
Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Polarity Control Input
E2
1.0/1.0
20 µA/−0.6 mA
OE
1.0/1.0
20 µA/−0.6 mA
P
1.0/1.0
20 µA/−0.6 mA
O0–O9
3-STATE Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Truth Table
Inputs
Outputs
Function
E1 E2 A3 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
OE
H
L
High Impedance
Disable
X
H
X
L
X
X
L
X
X
X
L
L
L
L
X
X
X
L
L
L
L
X
X
X
L
X
X
X
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Outputs Equal P Input
L
Active HIGH
Output
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
(P = L)
L
L
H
H
H
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
X
H
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Active LOW
Output
L
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
(P = H)
L
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
X
H
H
X
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
I
I
I
= −18 mA
CD
OH
IN
10% V
10% V
2.5
2.4
2.7
2.7
= −1 mA
= −3 mA
= −1 mA
= −3 mA
= 24 mA
= 2.7V
CC
CC
OH
OH
OH
OH
OL
Voltage
V
5% V
5% V
CC
CC
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
10% V
0.5
5.0
V
Min
OL
CC
I
I
µA
Max
V
IH
IN
BVI
7.0
50
µA
µA
V
Max
Max
0.0
V
= 7.0V
IN
I
CEX
V
= V
CC
OUT
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
I
I
I
I
I
I
Input LOW Current
Output Leakage Current
Output Leakage Current
−0.6
50
mA
µA
Max
Max
Max
Max
0.0V
Max
Max
V
V
V
V
V
V
V
= 0.5V
IN
IL
= 2.7V
= 0.5V
= 0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
−50
−150
500
56
µA
Output Short-Circuit Current
Bus Drainage Test
−60
mA
µA
= 5.25V
ZZ
Power Supply Current
Power Supply Current
mA
mA
= HIGH
CCH
CCZ
O
O
44
66
= HIGH Z
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4
AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
6.0
4.0
5.0
4.0
6.0
5.0
6.0
6.0
3.0
5.0
2.0
3.0
Typ
11.0
7.5
Max
16.0
11.0
14.5
9.0
Min
6.0
4.0
5.0
4.0
6.0
5.0
6.0
6.0
3.0
5.0
2.0
3.0
Max
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
to O
17.0
12.0
15.5
10.0
17.0
15.0
20.0
17.0
11.5
14.0
7.0
PLH
A
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
n
n
ns
ns
ns
Propagation Delay
to O
8.5
E
6.5
1
n
Propagation Delay
to O
11.0
10.0
11.5
11.0
5.5
16.0
14.0
18.0
16.0
10.5
13.0
6.0
E
2
n
Propagation Delay
P to O
n
Output Enable Time
OE to O
9.0
n
Output Disable Time
OE to O
4.0
5.0
7.0
8.0
n
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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