74F543SJC [FAIRCHILD]
Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO24, 0.300 INCH, EIAJ, PLASTIC, SOIC-24;
| 型号： | 74F543SJC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO24, 0.300 INCH, EIAJ, PLASTIC, SOIC-24 |
| 文件： | 总7页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised March 1999
74F543
Octal Registered Transceiver
General Description
Features
The F543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA.
■ 8-bit octal transceiver
■ Back-to-back registers for storage
■ Separate controls for data flow in each direction
■ A outputs sink 24 mA
■ B outputs sink 64 mA
Ordering Code:
Order Number Package Number
Package Description
74F543SC
M24B
MSA24
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F543MSA
74F543SPC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009554.prf
www.fairchildsemi.com
Unit Loading/Fan Out
U.L.
Input IIH/IIL
Pin Names
Description
HIGH/LOW
Output IOH/IOL
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
1.0/2.0
20 µA/−1.2 mA
1.0/2.0
20 µA/−1.2 mA
1.0/1.0
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
3.5/1.083
150/40 (33.8)
3.5/1.083
600/106.6 (80)
70 µA/−650 µA
B-to-A 3-STATE Outputs
−3 mA/24 mA (20 mA)
70 µA/−650 µA
B0–B7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
−12 mA/64 mA (48 mA)
Functional Description
Data I/O Control Table
The F543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A0–A7 or
Inputs
Latch
Output
Buffers
Status
CEAB LEAB OEAB
H
X
L
X
H
L
X
X
X
H
L
Latched
Latched
Transparent
—
High Z
—
take data from B0–B7, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
—
X
L
X
X
High Z
Driving
—
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
Input Clamp Diode Voltage
−1.2
Min
Min
Min
I
I
I
I
I
I
I
I
= −18 mA
CD
OH
IN
Output HIGH Voltage
10% V
2.5
2.4
2.7
2.7
2.0
= −1 mA (A )
n
CC
OH
OH
OH
OH
OH
OL
OL
10% V
= −3 mA (A , B )
n n
CC
5% V
5% V
V
V
= −1 mA (A )
n
CC
CC
= −3 mA (A , B )
n
n
10% V
10% V
10% V
= −15 mA (B )
n
CC
CC
CC
V
Output LOW
0.5
0.55
5.0
= 24 mA (A )
n
OL
Voltage
= 64 mA (B )
n
I
I
Input HIGH Current
Input HIGH Current
µA
µA
Max
Max
V
= 2.7V
IH
IN
7.0
(OEAB, OEBA, LEAB,
LEBA, CEAB, CEBA)
BVI
Breakdown Test
I
I
Input HIGH Current
Breakdown (I/O)
Output HIGH
0.5
50
mA
µA
V
Max
Max
0.0
V
= 5.5V (A , B )
n n
BVIT
CEX
IN
V
= V
OUT
CC
Leakage Current
Input Leakage
Test
V
4.75
I
= 1.9 µA
ID
ID
OD
IL
All Other Pins Grounded
= 150 mV
I
I
Output Leakage
Circuit Current
Input LOW Current
3.75
µA
mA
0.0
V
IOD
All Other Pins Grounded
−0.6
−1.2
Max
V
= 0.5V (OEAB, OEBA)
= 0.5V (CEAB, CEBA)
IN
V
V
V
V
V
V
V
V
V
IN
I
I
I
+ I
Output Leakage Current
Output Leakage Current
70
µA
µA
mA
Max
Max
Max
= 2.7V (A , B )
n n
IH
IL
OZH
OUT
OUT
OUT
OUT
OUT
+ I
−650
−150
−225
500
= 0.5V (A , B )
n n
OZL
Output Short-Circuit Current
−60
= 0V (A )
n
OS
−100
= 0V (B )
n
I
I
I
I
Bus Drainage Test
µA
mA
mA
mA
0.0V
Max
Max
Max
= 5.25V (A , B )
n n
ZZ
Power Supply Current
Power Supply Current
Power Supply Current
67
83
83
100
= HIGH
CCH
CCL
CCZ
O
O
O
125
= LOW
125
= HIGH Z
3
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AC Electrical Characteristics
T
= +25°C
A
V
= +5.0V
= 50 pF
T = 0°C to +70°C
A
CC
Symbol
Parameter
Units
C
C = 50 pF
L
L
Min
3.0
3.0
Typ
5.5
5.0
Max
7.5
Min
3.0
3.0
Max
t
t
Propagation Delay
Transparent Mode
to B or B to A
n
8.5
7.5
PLH
6.5
ns
ns
PHL
A
n
n
n
t
t
Propagation Delay
4.5
4.5
8.5
8.5
11.0
11.0
4.5
4.5
12.5
12.5
PLH
PHL
LEBA to A
n
t
t
Propagation Delay
4.5
4.5
8.5
8.5
11.0
11.0
4.5
4.5
12.5
12.5
ns
PLH
PHL
LEAB to B
n
t
t
Output Enable Time
PZH
PZL
3.0
4.0
7.0
7.5
9.0
3.0
4.0
10.0
12.0
OEBA or OEAB to A or B
n
n
n
10.5
ns
CEBA or CEAB to A or B
n
n
t
t
Output Disable Time
PHZ
PLZ
1.0
2.5
6.0
5.5
8.0
1.0
2.5
9.0
OEBA or OEAB to A or B
n
10.5
11.5
CEBA or CEAB to A or B
n
n
AC Operating Requirements
T
= +25°C
A
Symbol
Parameter
V
= +5.0V
T
= 0°C to +70°C
A
Units
ns
CC
Min
3.0
3.0
Max
Min
3.5
3.5
Max
t (H)
S
Setup Time, HIGH or LOW
or B to LEBA or LEAB
t (L)
S
A
n
n
t (H)
H
Hold Time, HIGH or LOW
or B to LEBA or LEAB
3.0
3.0
3.5
3.5
t (L)
H
A
n
n
t
(L)
Latch Enable, B to A or
B to A Pulse Width, LOW
8.0
9.0
ns
W
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4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Package Number N24A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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