74F646 [FAIRCHILD]
Octal Transceiver/Register with 3-STATE Outputs; 八路收发器/寄存器与3态输出
| 型号： | 74F646 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Transceiver/Register with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1988
Revised August 1999
74F646 • 74F646B • 74F648
Octal Transceiver/Register with 3-STATE Outputs
General Description
Features
These devices consist of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control G is Active LOW.
In the isolation mode (control G HIGH), A data may be
stored in the B register and/or B data may be stored in the
A register.
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ 74F648 has inverting data paths
■ 74F646/74F646B have non-inverting data paths
■ 74F646B is a faster version of the 74F646
■ 3-STATE outputs
■ 300 mil slim DIP
Ordering Code:
Order Number Package Number
Package Description
74F646SC
M24B
MSA24
N24C
M24B
N24C
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F646MSA
74F646SPC
74F646BSC
74F646BSPC
74F648SC
74F648SPC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS009580
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Logic Symbols
74F646/74F646B
74F648
IEEE/IEC
74F646/74F646B
IEEE/IEC
74F648
Connection Diagrams
74F646/74F646B
74F648
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2
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
A0–A7
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
70 µA/−650 µA
−12 mA/64 mA (48 mA)
70 µA/−650 µA
B0–B7
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
CPAB, CPBA
SAB, SBA
1.0/1.0
20 µA/−0.6 mA
Output Enable Input
1.0/1.0
20 µA/−0.6 mA
G
DIR
Direction Control Input
1.0/1.0
20 µA/−0.6 mA
Function Table
Inputs
Data I/O (Note 1)
A0–A7 B0–B7
Function
G
H
H
H
L
DIR CPAB CPBA SAB SBA
X
X
X
H
H
H
H
L
H or L H or L
X
X
X
L
X
X
X
X
X
X
X
L
Isolation
X
Input
Input Clock An Data into A Register
Clock Bn Data into B Register
X
X
X
X
X
X
X
An to Bn—Real Time (Transparent Mode)
Output Clock An Data into A Register
A Register to Bn (Stored Mode)
L
L
Input
L
H or L
H
H
X
X
X
X
L
Clock An Data into A Register and Output to Bn
Bn to An—Real Time (Transparent Mode)
Input Clock Bn Data into B Register
B Register to An (Stored Mode)
L
X
X
X
X
L
L
L
Output
L
L
H or L
H
H
L
L
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Irrelevant
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
3
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Logic Diagrams
74F646/74F646B
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F648
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
= −18 mA (Non I/O Pins)
CD
OH
IN
10% V
10% V
2.0
V
V
I
= −15 mA (A , B )
OH n n
CC
Voltage
V
Output LOW
OL
0.55
5.0
7.0
0.5
50
Min
Max
Max
Max
Max
0.0
I
= 64 mA (A , B )
OL n n
CC
Voltage
I
Input HIGH
IH
µA
µA
mA
µA
V
V
V
V
V
= 2.7V (Non I/O Pins)
= 7.0V (Non I/O Pins)
IN
Current
I
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
BVI
IN
I
BVIT
= 5.5V (A , B )
IN
n
n
I
CEX
= V
OUT
CC
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
−0.6
70
mA
µA
Max
Max
Max
Max
0.0V
Max
Max
Max
V
V
V
V
V
V
V
V
= 0.5V (Non I/O Pins)
IL
IN
I
+ I
= 2.7V (A , B )
n n
IH
OZH
OUT
OUT
OUT
OUT
I
+ I
−650
−225
500
135
150
150
µA
= 0.5V (A , B )
n n
IL
OZL
I
−100
mA
µA
= 0V
OS
I
= 5.25V
ZZ
I
mA
mA
mA
= HIGH
CCH
O
O
O
I
= LOW
= HIGH Z
CCL
I
CCZ
5
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AC Electrical Characteristics 74F646/74F648
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
90
Max
Min
75
Max
Min
90
Max
f
t
t
t
t
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
Clock to Bus
MHz
ns
MAX
2.0
2.0
1.0
1.0
2.0
1.0
2.0
2.0
2.0
2.0
7.0
8.0
7.0
6.5
8.5
7.5
8.5
8.0
8.5
12.0
2.0
2.0
1.0
1.0
1.0
1.0
2.0
2.0
2.0
2.0
8.5
9.5
2.0
2.0
1.0
1.0
2.0
1.0
2.0
2.0
2.0
2.0
8.0
9.0
7.5
7.0
9.0
8.0
9.5
9.0
9.0
12.5
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
Propagation Delay
Bus to Bus (74F646)
Propagation Delay
Bus to Bus (74F648)
Propagation Delay
SBA or SAB to A or B
Enable Time
8.0
ns
ns
ns
ns
8.0
10.0
9.0
11.0
10.0
10.0
13.5
OE to A or B
Disable Time
t
t
1.0
2.0
7.5
9.0
1.0
2.0
9.0
1.0
2.0
8.5
9.5
PHZ
PLZ
ns
ns
ns
11.0
OE to A or B
Enable Time
DIR to A or B
Disable Time
DIR to A or B
t
t
t
t
2.0
2.0
1.0
2.0
14.0
13.0
9.0
2.0
2.0
1.0
2.0
16.0
15.0
10.0
12.0
2.0
2.0
1.0
2.0
15.0
14.0
9.5
PZH
PZL
PHZ
PLZ
11.0
11.5
AC Operating Requirements 74F646/74F648
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
5.0
5.0
2.0
2.0
5.0
5.0
Max
Min
5.0
5.0
2.5
2.5
5.0
5.0
Max
Min
5.0
5.0
2.0
2.0
5.0
5.0
Max
t (H)
Setup Time, HIGH or LOW
Bus to Clock
S
ns
ns
ns
t (L)
S
t
(H)
(L)
Hold Time, HIGH or LOW
Bus to Clock
H
t
H
t
(H)
(L)
Clock Pulse Width
HIGH or LOW
W
t
W
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AC Electrical Characteristics 74F646B
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
165
2.5
3.0
2.0
2.0
2.5
2.5
2.5
2.5
Max
Min
Max
Min
150
2.5
3.0
2.0
2.0
2.5
2.5
2.5
2.5
Max
f
t
t
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
Clock to Bus
MHz
ns
MAX
7.0
7.5
6.0
6.0
7.5
7.5
6.5
9.0
8.0
8.0
7.0
7.0
8.5
8.5
8.0
10.0
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
Propagation Delay
Bus to Bus
ns
ns
ns
Propagation Delay
SBA or SAB to A or B
Enable Time
OE to A or B
Disable Time
t
t
1.5
2.0
6.5
7.0
1.5
2.0
7.5
8.5
PHZ
PLZ
ns
ns
ns
OE to A or B
Enable Time
DIR to A or B
Disable Time
DIR to A or B
t
t
t
t
2.0
3.0
1.5
2.5
7.0
9.5
7.5
8.5
2.0
3.0
1.5
2.5
8.5
10.0
8.5
PZH
PZL
PHZ
PLZ
9.5
AC Operating Requirements 74F646B
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
5.0
5.0
1.5
1.5
5.0
5.0
Max
Min
Max
Min
4.0
4.0
1.5
1.5
5.0
5.0
Max
t (H)
Setup Time, HIGH or LOW
Bus to Clock
S
ns
ns
ns
t (L)
S
t
t
t
t
(H)
Hold Time, HIGH or LOW
Bus to Clock
H
(L)
H
(H)
(L)
Clock Pulse Width
HIGH or LOW
W
W
7
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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