74F646A [NXP]
Octal transceiver/register, non-inverting 3-State; 八路收发器/寄存器，非反相三态
| 型号： | 74F646A |
| 厂家： | 
NXP |
| 描述： | Octal transceiver/register, non-inverting 3-State |
| 文件： | 总16页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F646, 74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648, 74F648A
Octal transceiver/register, inverting
(3-State)
Product specification
IC15 Data Handbook
1990 Sep 25
Philips
Semiconductors
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
FEATURES
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3–state outputs, D–type
flip–flops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE) and DIR pins are provided
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
• Combines 74F245 and two 74F374 type functions in one chip
• High impedance base inputs for reduced loading (70µA in high
and low states)
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of non-inverting and inverting data paths
• Controlled ramp outputs for 74F646A/74F648A
• 3-state outputs
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE is active low. In the
isolation mode (OE = high), data from bus A may be stored in the B
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
• 300 mil wide 24-pin slim dip package
TYPE
TYPICAL f
TYPICAL SUPPLY CURRENT ( TOTAL)
max
74F646/74F648
74F646A/74F648A
115MHz
185MHz
140mA
105mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
PKG DWG #
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
24–pin plastic slim DIP
(300mil)
N74F646N, N74F646AN, N74F648N, N74F648AN
SOT222-1
SOT137-1
24–pin plastic SOL
N74F646D, N74F646AD, N74F648D, N74F648AD
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
PINS
DESCRIPTION
A0 – A7, B0 – B7
A and B inputs
3.5/0.116
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
750/80
70µA/70µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
15mA/48mA
15mA/64mA
CPAB
A–to–B clock input
B–to–A clock input
A–to–B select input
B–to–A select input
CPBA
SAB
SBA
DIR
Data flow directional control enable input
Output enable input
OE
A0 – A7, B0 – B7
A0 – A7, B0 – B7
A, B outputs for N74F646A/N74F648A
A, B outputs for N74F646/N74F648
750/106.7
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
1990 Sep 25
853-1124 00515
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
PIN CONFIGURATION
IEC/IEEE SYMBOL
74F646/646A
74F646/646A
21
3
G3
1
2
3
4
5
24
23
22
21
20
CPAB
SAB
DIR
A0
V
CC
3 EN1 [BA]
3 EN2 [AB]
CPBA
SBA
OE
B0
23
22
1
C4
G5
A1
C6
G7
2
6
7
19
18
17
16
15
14
13
B1
A2
B2
A3
20
1
1
5
5
4D
4
8
B3
A4
1
9
B4
A5
7
7
1
6D
2
1
10
11
12
B5
A6
5
19
B6
6
A7
18
17
16
15
14
13
7
B7
GND
8
SF00386
9
/
10
11
LOGIC SYMBOL
SF00388
74F646/646A
4
5
6
7
8
9
10 11
LOGIC DIAGRAM
74F646/646A
A0 A1 A2 A3 A4 A5 A6 A7
21
OE
CPAB
SAB
DIR
1
2
3
DIR
3
23
CPBA
22
CPBA
SBA
OE
23
22
21
SBA
1
CPAB
2
SAB
B0 B1 B2 B3 B4 B5 B6 B7
I of 8 channels
1D
C1
20 19 18 17 16 15 14 13
SF00387
V
= Pin 24
CC
GND = Pin 12
4
20
A0
B0
1D
C1
V
= Pin 24
CC
to 7 other channels
SF00393
GND = Pin 12
3
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
PIN CONFIGURATION
IEC/IEEE SYMBOL
74F648/648A
74F648/648A
21
3
G3
1
2
3
4
5
24
23
22
21
20
CPAB
SAB
DIR
A0
V
CC
3 EN1 [BA]
3 EN2 [AB]
CPBA
SBA
OE
B0
23
22
1
C4
G5
C6
G7
A1
2
6
7
19
18
17
16
15
14
13
B1
A2
20
B2
A3
1
1
5
5
4D
4
1
1
8
B3
A4
7
7
6D
9
B4
A5
2
1
10
11
12
B5
5
A6
19
6
18
17
16
15
14
13
B6
A7
7
B7
GND
8
SF00389
9
10
11
LOGIC SYMBOL
SF00391
74F648/648A
4
5
6
7
8
9
10 11
LOGIC DIAGRAM
74F648/648A
21
A0 A1 A2 A3 A4 A5 A6 A7
OE
CPAB
SAB
DIR
1
2
3
DIR
23
CPBA
22
3
CPBA
SBA
OE
23
22
21
SBA
1
CPAB
2
SAB
B0 B1 B2 B3 B4 B5 B6 B7
I of 8 channels
1D
C1
20 19 18 17 16 15 14 13
SF00390
V
= Pin 24
CC
GND = Pin 12
4
20
A0
B0
1D
C1
to 7 other channels
SF00400
4
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OE
X
DIR
X
CPAB CPBA SAB
SBA
X
An
Input
Bn
74F646/74F646A
74F648/74F648A
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
↑
X
↑
X
↑
X
X
X
X
X
X
L
Unspecified*
Input
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
X
X
X
Unspecified*
Input
H
H
L
X
↑
X
Input
X
H or L H or L
X
Input
Input
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
L
X
X
X
H or L
X
L
Output
Output
Input
Input
L
L
H
Input
L
H
H
X
X
Output
Output
L
H or L
X
H
X
Input
NOTES:
1. H = High–voltage level
2. L
3. X
4. ↑
5. *
=
=
=
=
Low–voltage level
Don’t care
Low–to–high clock transition
The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every low–to–high transition of the clock.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
74F646A, 74F648A
74F646, 74F648
72
mA
mA
°C
°C
OUT
128
Operating free air temperature range
Storage temperature range
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
V
0.8
–18
–15
48
V
I
I
I
mA
mA
mA
mA
Ik
High–level output current
Low–level output current
OH
OL
74F646A, 74F648A
74F646, 74F648
64
T
amb
Operating free air temperature range
0
+70
°C
5
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
The following examples demonstrate the four fundamental
bus–management functions that can be performed with the
74F646/646A and 74F648/648A. The select pins determine whether
data is stored or transferred through the device in real time. The
output enable pins determine the direction of the data flow.
BUS MANAGEMENT FUNCTIONS
STORAGE FROM
A, B, OR A AND B
REAL TIME BUS TRANSFER
BUS A TO BUS B
TRANSFER STORED DATA
TO A AND/OR B
REAL TIME BUS TRANSFER
BUS B TO BUS A
BUS A
BUS A
BUS A
BUS B
BUS B
BUS A
BUS B
BUS B
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
X
X
H
X
X
X
↑
X
↑
X
↑
↑
X
X
X
X
X
X
L
L
L
H
X
H or L
X
X
H
H
X
L
L
X
X
X
L
H or L
SF00392
6
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN
TYP
MAX
±10%V
±5%V
V
= MIN,
I
= –3mA
2.4
V
V
CC
CC
OH
V
OH
High-level output voltage
V
V
= MAX,
2.7
2.0
3.4
CC
IL
I
=
OH
±10%V
= MIN
V
CC
IH
–15mA
V
V
= MIN,
= MAX,
CC
IL
V
V
Low-level output voltage
All
I
= 48mA ±10%V
0.38
0.55
0.55
V
V
OL
OL
OL
CC
74F646/74F648 only
V
IH
= MIN
I
= 64mA
±5%V
0.42
CC
Input clamp voltage
Input current at
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73
-1.2
100
1
V
IK
I
I
I
others
= 0.0V, V = 7.0V
µA
mA
µA
µA
I
maximum input voltage
High–level input current
Low–level input current
A0–A7, B0–B7
OE, DIR, CPAB,
CPBA, SAB, SBA
= MAX, V = 5.5V
I
I
I
= MAX, V = 2.7V
20
IH
I
= MAX, V = 0.5V
–20
IL
I
Off–state output current,
high–level voltage applied
µA
µA
I
I
+ I
V
V
= MAX, V = 2.7V
70
OZH
IH
CC
O
A0 – A7, B0 –B7
Off–state output current,
low–level voltage applied
+ I
= MAX, V = 0.5V
–70
OZL
IL
CC
O
3
I
I
Short–circuit output current
74F646, 74F648
V
V
= MAX
-100
-60
-225
-150
165
210
160
145
155
155
mA
mA
mA
mA
mA
mA
mA
mA
OS
CC
4
Output current
74F646A, 74F648A
= MAX, V = 2.25V
O
CC
0
74F646,
74F648
I
125
160
135
100
110
105
CCH
I
V
CC
= MAX
CCL
CCZ
CCH
I
Supply current (total)
I
CC
74F646A,
74F648A
I
I
V
CC
= MAX
CCL
I
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, V = V for all test conditions.
X
CC
2. All typical values are at V = 5V, T
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
= 25°C.
CC
amb
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. I is tested under conditions that produce current approximately one half of the true short–circuit output current (I ).
O
OS
7
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F646
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
100
115
90
MHz
ns
max
t
t
Propagation delay
CPAB or CPBA to An or Bn
5.5
5.5
7.5
8.0
10.0
10.0
5.0
5.0
11.5
11.0
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
4.0
4.0
6.0
6.5
9.0
8.0
4.0
4.0
10.0
10.0
PLH
PHL
Waveform 2
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB or SBA to An or Bn
5.0
5.0
7.0
6.5
8.5
8.5
4.5
4.5
10.5
9.5
PLH
PHL
Waveform 2, 3
t
t
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
5.0
6.5
7.0
8.5
10.0
11.0
4.5
6.0
11.0
12.5
PZH
PZL
t
t
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
4.5
6.0
6.5
8.5
9.0
11.0
4.0
5.5
10.0
12.5
PZH
PZL
t
t
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
6.5
6.5
9.0
9.0
11.5
11.5
6.0
6.0
12.5
13.5
PHZ
PLZ
t
t
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
5.5
5.5
8.5
8.5
11.0
11.0
4.5
5.0
13.0
12.5
PHZ
PLZ
AC SETUP REQUIREMENTS FOR 74F646
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
4.5
4.5
5.0
5.0
su
su
Waveform 4
Waveform 4
Waveform 1
ns
ns
ns
t (H)
Hold time, high or low
An or Bn to CPAB or CPBA
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
Pulse width, high or low
CPAB or CPBA
4.0
6.0
4.0
6.0
8
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F648
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
100
115
90
MHz
ns
max
t
t
Propagation delay
CPAB or CPBA to An or Bn
5.0
5.0
7.0
7.5
9.5
9.5
4.5
4.5
11.0
11.0
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
3.0
4.0
6.0
6.0
8.5
8.5
2.5
3.5
9.5
9.5
PLH
PHL
Waveform 3
Waveform 2,3
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB or SBA to An or Bn
4.5
4.5
7.0
6.5
8.5
8.5
4.5
4.5
10.5
9.5
PLH
PHL
t
t
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
4.5
6.0
7.0
8.5
10.0
11.0
4.5
5.5
11.0
12.5
PZH
PZL
t
t
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
4.5
6.0
7.0
8.5
10.0
11.0
4.0
5.5
11.0
12.5
PZH
PZL
t
t
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
6.0
6.0
9.0
8.5
11.5
12.0
6.0
6.0
12.5
13.5
PHZ
PLZ
t
t
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
5.0
5.0
9.0
9.0
12.5
12.5
4.5
5.0
14.0
14.0
PHZ
PLZ
AC SETUP REQUIREMENTS FOR 74F648
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
4.0
4.0
5.0
5.0
su
su
Waveform 4
Waveform 4
Waveform 1
ns
ns
ns
t (H)
Hold time, high or low
An or Bn to CPAB or CPBA
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
Pulse width, high or low
CPAB or CPBA
3.5
6.5
4.0
7.0
9
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F646A
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
165
185
150
MHz
ns
max
t
t
Propagation delay
CPAB or CPBA to An or Bn
5.5
4.5
7.0
7.0
10.5
9.5
4.5
4.0
11.0
10.0
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
4.0
2.0
6.0
5.0
9.0
8.0
3.5
2.0
10.0
8.0
PLH
PHL
Waveform 2
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB or SBA to An or Bn
4.5
3.5
6.5
8.0
9.5
10.0
4.0
3.0
10.0
11.5
PLH
PHL
Waveform 2, 3
t
t
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.0
3.0
5.5
5.5
9.0
10.0
2.5
2.5
10.0
10.5
PZH
PZL
t
t
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.0
3.5
5.0
6.0
8.0
8.5
3.0
3.0
8.5
9.5
PZH
PZL
t
t
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
1.5
2.5
4.0
5.5
6.5
8.0
1.0
2.0
8.0
9.5
PHZ
PLZ
t
t
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.0
3.0
4.5
5.0
7.5
8.0
1.5
2.0
8.5
8.5
PHZ
PLZ
AC SETUP REQUIREMENTS FOR 74F646A
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
3.5
4.0
4.0
4.5
su
su
Waveform 4
Waveform 4
Waveform 1
ns
ns
ns
t (H)
Hold time, high or low
An or Bn to CPAB or CPBA
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
Pulse width, high or low
CPAB or CPBA
3.5
3.5
4.5
4.0
10
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F648A
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
160
185
135
ns
ns
max
t
t
Propagation delay
CPAB or CPBA to An or Bn
5.0
5.5
7.0
7.5
9.5
10.0
4.5
4.5
10.5
10.5
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
2.5
4.0
4.5
6.0
7.5
8.5
2.0
4.0
8.5
9.5
PLH
PHL
Waveform 3
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB or SBA to An or Bn
4.0
4.5
7.0
7.0
9.5
9.5
3.5
4.5
11.5
10.0
PLH
PHL
Waveform 2, 3
t
t
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.5
4.5
6.5
6.5
10.0
10.0
3.5
4.0
11.0
11.5
PZH
PZL
t
t
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.5
4.0
5.5
6.5
8.5
9.5
3.0
4.0
9.0
10.0
PZH
PZL
t
t
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
2.5
4.0
4.0
6.5
6.5
9.0
2.0
3.5
8.0
10.0
PHZ
PLZ
t
t
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.5
2.5
5.0
5.0
8.5
8.0
2.0
3.5
9.0
9.0
PHZ
PLZ
AC SETUP REQUIREMENTS FOR 74F648A
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
An or Bn to CPAB or CPBA
4.0
4.0
4.5
4.5
su
su
Waveform 4
Waveform 4
Waveform 1
ns
ns
ns
t (H)
Hold time, high or low
An or Bn to CPAB or CPBA
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
Pulse width, high or low
CPAB or CPBA
3.5
3.5
4.0
3.5
AC WAVEFORMS
1/f
max
An or Bn
SBA or SAB
V
CPBA
or
CPAB
V
M
M
V
V
t
(H)
M
V
M
t
w
M
t
t
PLH
PHL
t
t
(L)
PLH
PHL
w
V
V
M
M
V
V
M
M
Bn or An
An or Bn
SF00395
An or Bn
SF00394
Waveform 2. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
Waveform 1. Propagation delay for clock input to output clock
pulse width, and maximum clock frequency
11
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC WAVEFORMS (Continued)
OE
V
V
M
M
SBA or SAB
An or Bn
V
V
M
M
DIR
V
-0.3V
0V
OH
t
t
PHZ
PZH
t
t
PHL
PLH
An or Bn
V
M
An or Bn
Bn or An
V
V
M
M
SF00398
SF00396
Waveform 5. 3-state output enable time to high level and
output disable time from high level
Waveform 3. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
OE
V
V
M
M
DIR
An or Bn
V
V
V
V
M
M
M
M
t
t
PLZ
PZL
3.5V
t
(L)
t (L)
h
t
(H)
t (H)
h
su
su
V
M
An or Bn
CPBA
or
CPAB
V
M
V
M
V
+0.3V
OL
SF00399
SF00397
Waveform 6. 3-state output enable time to low level and output
disable time from low level
Waveform 4. Data setup time and hold times
NOTES:
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORM
V
CC
t
AMP (V)
0V
w
7.0V
90%
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
t
SWITCH POSITION
TEST
w
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
12
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
13
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
14
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
NOTES
15
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05151
Document order number:
Philips
Semiconductors
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