74F657 [FAIRCHILD]
Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs; 八路双向收发器，具有8位奇偶校验发生器/校验器和三态输出
| 型号： | 74F657 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs |
| 文件： | 总7页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1988
Revised August 1999
74F657
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
Features
■ 300 Mil 24-pin slimline DIP
The 74F657 contains eight non-inverting buffers with 3-
STATE outputs and an 8-bit parity generator/checker. It is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 24 mA at the A
Port and 64 mA at the B Port.
■ Combines 74F245 and 74F280A functions in one
package
■ 3-STATE outputs
■ B Outputs sink 64 mA
■ 12 mA source current, B side
■ Input diodes for termination effects
Ordering Code:
Order Number Package Number
Package Description
75F657SC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F657SPC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009584
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
4.5/0.15
A0–A7
Data Inputs/
90 µA/− 90 µA
−3 mA/24 mA (20 mA)
70 µA/−70 µA
3-STATE Outputs
Data Inputs/
150/40 (33.3)
3.5/0.117
B0–B7
3-STATE Outputs
Transmit/Receive Input
Enable Input
600/106.6 (80)
2.0/0.067
−12 mA/64 mA (48 mA)
40 µA/−40 µA
T/R
OE
2.0/0.067
40 µA/−40 µA
PARITY
Parity Input/
3.5/0.117
70 µA/−70µA
3-STATE Output
ODD/EVEN Parity Input
Error Output
600/106.6 (80)
1.0/0.033
−12 mA/64 mA (48 mA)
20 µA/−20 µA
ODD/EVEN
ERROR
600/106.6 (80)
−12 mA/64 mA (48 mA)
Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A Port to the
B Port; Receive (active LOW) enables data from the B Port
to the A Port.
select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B Ports by placing
them in a HIGH-Z condition when the Output Enable input
is HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A Port are
HIGH and compares these with the condition of the parity
Function Table
Function Table
Input/
Inputs
Inputs
Outputs
Number of
Inputs that
are HIGH
Outputs
Output
OE
L
T/R
L
ODD/
Outputs
Mode
OE T/R
Parity ERROR
Bus B Data to Bus A
Bus A Data to Bus B
High-Z State
EVEN
L
H
0, 2, 4, 6, 8
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
H
L
Z
Z
H
L
Transmit
Transmit
Receive
Receive
Receive
Receive
Transmit
Transmit
Receive
Receive
Receive
Receive
Z
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
H
H
L
H
L
L
L
H
L
L
L
L
H
Z
Z
L
1, 3, 5, 7
H
H
L
H
L
L
H
H
L
H
H
L
L
H
H
L
L
H
L
L
L
Immaterial
X
X
Z
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Functional Block Diagram
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
V
V
V
Input LOW Voltage
0.8
IL
Input Clamp Diode Voltage
−1.2
Min
Min
I
I
= −18 mA
CD
OH
IN
Output HIGH
Voltage
10% V
2.5
2.4
2.0
= −1 mA (A )
CC
OH
n
10% V
10% V
5% V
I
= −3 mA (A B , Parity, ERROR)
CC
OH
n
n
V
I
I
= −15 mA (B , Parity, ERROR)
n
CC
CC
OH
OH
2.7
2.7
= −1 mA (A )
n
5% V
I
I
= −3 mA (A , B , Parity, ERROR)
CC
OH
OL
n
n
V
Output LOW
Voltage
10% V
10% V
0.5
= 24 mA (A )
n
OL
CC
V
Min
0.55
I
= 64 mA (B Parity, ERROR)
CC
OL
n
I
Input HIGH
Current
20
40
V
V
= 2.7V (ODD/EVEN)
IH
IN
IN
µA
Max
2.7V (T/R, OE)
I
Input HIGH Current
Breakdown Test
BVI
100
µA
V
= 0
V
= 7.0V (T/R, OE, ODD/EVEN)
CC
IN
I
Input HIGH Current
Breakdown Test (I/O)
1.0
2.0
V
V
V
= 5.5V (Parity, B )
n
BVIT
IN
IN
mA
Max
= 5.5V (A )
n
I
Input LOW
Current
−20
−40
= 0.5V (ODD/EVEN)
= 0.5V (T/R, OE)
IL
IN
IN
µA
Max
V
V
I
Output Leakage Current
50
µA
µA
Max
Max
= 2.7V (ERROR)
OZH
OUT
OUT
I
Output Leakage Current
Output Leakage
Current
−50
70
V
V
V
V
V
V
= 0.5V (ERROR)
OZL
I
+ I
= 2.7V (B , Parity)
I/O n
IH
OZH
µA
µA
Max
Max
Max
90
= 2.7V (A )
n
I/O
I
+ I
Output Leakage
Current
−70
−90
−150
−225
= 0.5V (B , Parity)
I/O n
IL
OZL
= 0.5V (A )
I/O
n
I
Output Short-Circuit
Current
−60
= 0V (A )
OUT n
OS
mA
−100
V
= 0V (B , Parity, ERROR)
OUT
n
I
Output HIGH Leakage
Current
250
1.0
2.0
µA
mA
mA
Max
Max
Max
V
V
V
= V (ERROR)
CEX
OUT
OUT
OUT
CC
= V (B , Parity)
CC
n
= V (A )
CC
n
I
Bus Drainage Test
500
125
150
145
µA
mA
mA
mA
0.0V
Max
Max
Max
V
V
V
V
= 5.25V (A , B , Parity, ERROR)
OUT n n
ZZ
I
Power Supply Current
Power Supply Current
Power Supply Current
101
112
109
= HIGH
CCH
O
O
O
I
= LOW
CCL
I
= HIGH Z
CCZ
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4
AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
2.5
3.0
6.5
7.0
4.5
4.5
Typ
4.5
Max
8.0
Min
2.5
3.0
5.5
5.5
4.0
4.5
Max
Min
2.5
3.0
6.0
6.0
4.0
4.5
Max
t
t
t
t
t
t
Propagation Delay
to B , B to A
9.5
8.5
9.0
8.0
PLH
ns
ns
ns
A
4.9
7.5
PHL
PLH
PHL
PLH
PHL
n
n
n
n
Propagation Delay
to Parity
10.1
10.9
7.8
14.0
15.0
11.0
12.0
18.0
20.5
14.0
16.5
16.0
16.5
13.0
13.5
A
n
Propagation Delay
8.8
ODD/EVEN to PARITY
Propagation Delay
t
t
4.5
4.5
7.5
8.2
11.0
12.0
4.0
4.5
14.0
16.5
4.0
4.5
13.0
13.5
PLH
PHL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ODD/EVEN to ERROR
Propagation Delay
t
t
8.0
8.0
14.0
15.0
20.5
21.5
7.5
7.5
27.0
28.5
7.5
7.5
23.0
23.5
PLH
PHL
B
to ERROR
n
t
t
Propagation Delay
7.0
7.5
10.8
11.8
15.5
16.5
6.0
6.5
20.0
22.0
6.0
7.5
17.0
18.5
PLH
PHL
PARITY to ERROR
Output Enable Time
t
t
3.0
4.0
5.0
6.5
8.0
2.5
3.5
11.0
13.5
2.5
3.5
9.5
PZH
PZL
10.0
11.0
OE to A /B
n
n
t
t
Output Disable Time
OE to A /B
1.0
1.0
4.5
4.9
8.0
7.5
1.0
1.0
9.5
8.5
1.0
1.0
9.0
8.0
PHZ
PLZ
n
n
t
t
Output Enable Time
3.0
4.0
5.0
7.7
8.0
2.5
3.5
11.0
13.5
2.5
3.5
9.5
PZH
PZL
10.0
11.0
OE to ERROR (Note 3)
Output Disable Time
t
t
1.0
1.0
4.5
4.9
8.0
7.5
1.0
1.0
9.5
8.5
1.0
1.0
9.0
8.0
PHZ
PLZ
OE to ERROR
t
t
Output Enable Time
3.0
4.0
5.0
7.7
8.0
2.5
3.5
11.0
13.5
2.5
3.5
9.5
PZH
PZL
10.0
11.0
OE to PARITY
t
t
Output Disable Time
1.0
1.0
4.6
5.1
8.0
7.5
1.0
1.0
9.5
8.5
1.0
1.0
9.0
8.0
PHZ
PLZ
OE to PARITY
Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output
Enable Time).
5
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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