74F675A_00 [FAIRCHILD]
16-Bit Serial-In, Serial/Parallel-Out Shift Register; 16位串行输入，串行/并行输出移位寄存器
| 型号： | 74F675A_00 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Serial-In, Serial/Parallel-Out Shift Register |
| 文件： | 总6页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised October 2000
74F675A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
Features
The 74F675A contains a 16-bit serial in/serial out shift reg-
ister and a 16-bit parallel out storage register. Separate
serial input and output pins are provided for expansion to
longer words. By means of a separate clock, the contents
of the shift register are transferred to the storage register.
The contents of the storage register can also be loaded
back into the shift register. A HIGH signal on the Chip
Select input prevents both shifting and parallel loading.
■ Serial-to-parallel converter
■ 16-Bit serial I/O shift register
■ 16-Bit parallel out storage register
■ Recirculating parallel transfer
■ Expandable for longer words
■ Slim 24 lead package
■ 74F675A version prevents false clocking through
CS or R/W inputs
Ordering Code:
Order Number Package Number
Package Description
74F675ASC
74F675APC
74F675ASPC
M24B
N24A
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS009587
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
SI
Serial Data Input
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
CS
Chip Select Input (Active LOW)
Shift Clock Pulse Input (Active Falling Edge)
Store Clock Pulse Input (Active Rising Edge)
Read/Write Input
1.0/1.0
SHCP
STCP
R/W
SO
1.0/1.0
1.0/1.0
1.0/1.0
Serial Data Output
50/33.3
50/33.3
Q0–Q15
Parallel Data Outputs
Functional Description
The 16-Bit shift register operates in one of four modes, as
determined by the signals applied to the Chip Select (CS),
Read/Write (R/W) and Store Clock Pulse (STCP) input.
State changes are indicated by the falling edge of the Shift
Clock Pulse (SHCP). In the Shift Right mode, data enters
The storage register is in the Hold mode when either CS or
R/W is HIGH. With CS and R/W both LOW, the storage
register is parallel loaded from the shift register on the ris-
ing edge of STCP.
To prevent false clocking of the shift register, SHCP should
be in the LOW state during a LOW-to-HIGH transition of
CS. To prevent false clocking of the storage register, STCP
should be LOW during a HIGH-to-LOW transition of CS if
D
0 from the Serial Input (SI) pin and exits from Q15 via the
Serial Data Output (SO) pin. In the Parallel Load mode,
data from the storage register outputs enter the shift regis-
ter and serial shifting is inhibited.
R/W is LOW, and should also be LOW during
HIGH-to-LOW transition of R/W if CS is LOW.
a
Shift Register Operations Table
Storage Register Operations Table
Control Inputs
Operating
Mode
Inputs
Operating
Mode
CS
H
L
R/W SHCP STCP
CS
H
R/W
X
STCP
X
L
X
X
X
L
Hold
X
X
Hold
Shift Right
Shift Right
Parallel Load,
No Shifting
L
H
Hold
L
H
H
L
L
Parallel Load
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
L
H
= HIGH-to-LOW Transition
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
VCD
VOH
−1.2
Min
Min
I
I
I
IN = −18 mA
OH = −1 mA
OH = −1 mA
10% VCC
5% VCC
2.5
2.7
V
V
Voltage
VOL
Output LOW
10% VCC
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
OL = 20 mA
Voltage
IIH
Input HIGH
µA
µA
µA
V
V
V
V
IN = 2.7V
IN = 7.0V
OUT = VCC
Current
IBVI
ICEX
VID
IOD
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
I
ID = 1.9 µA
All Other Pins Grounded
IOD = 150 mV
All Other Pins Grounded
4.75
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
V
3.75
µA
0.0
IIL
−0.6
−150
160
mA
mA
mA
mA
Max
Max
Max
Max
V
V
V
V
IN = 0.5V
OUT = 0V
O = HIGH
O = LOW
IOS
ICCH
ICCL
−60
106
106
160
3
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AC Electrical Characteristics
T
A = +25°C
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
Max
V
CC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
Min
100
3.0
3.0
4.0
4.5
Typ
130
8.0
Max
Min
85
fMAX
Maximum Clock Frequency
MHz
ns
tPLH
tPHL
tPLH
tPHL
Propagation Delay
STCP to Qn
10.5
13.5
9.5
2.5
2.5
3.5
4.0
12.0
15.0
10.5
12.0
10.5
7.0
Propagation Delay
SHCP to SO
ns
8.0
10.5
AC Operating Requirements
T
A = +25°C
CC = +5.0V
Max
T
A = 0°C to +70°C
CC = +5.0V
Max
Symbol
Parameter
V
V
Units
Min
3.5
5.5
0
Min
4.0
6.5
0
tS(H)
Setup Time, HIGH or LOW
CS or R/W to STCP
Hold Time, HIGH or LOW
CS or R/W to STCP
Setup Time, HIGH or LOW
SI to SHCP
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
ns
0
0
3.0
3.0
3.0
3.0
6.5
9.0
0
3.5
3.5
3.5
3.5
7.5
ns
ns
ns
ns
Hold Time, HIGH or LOW
SI to SHCP
Setup Time, HIGH or LOW
R/W to SHCP
10.0
0
Hold Time, HIGH or LOW
R/W to SHCP
0
0
Setup Time, HIGH or LOW
STCP to SHCP
7.0
7.0
0
8.0
8.0
0
Hold Time, HIGH or LOW
STCP to SHCP
0
0
Setup Time, HIGH or LOW
CS to SHCP
3.0
3.0
3.0
3.0
3.5
3.5
3.5
3.5
Hold Time, HIGH or LOW
CS to SHCP
tW(H)
SHCP Pulse Width
HIGH or LOW
5.0
5.0
6.0
5.0
6.0
6.0
7.0
6.0
t
W(L)
ns
tW(H)
tW(L)
STCP Pulse Width
HIGH or LOW
tS(L)
tH(H)
SHCP to STCP
SHCP to STCP
8.0
0.0
9.0
0.0
ns
ns
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4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
Package Number N24A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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