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74F794PC [FAIRCHILD]

8-Bit Register with Readback; 8位寄存器回读
74F794PC
型号： 74F794PC
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

8-Bit Register with Readback
8位寄存器回读

触发器 锁存器 逻辑集成电路 光电二极管
文件： 总6页 (文件大小：53K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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March 1990  
Revised August 1999  
74F794  
8-Bit Register with Readback  
General Description  
Features  
The 74F794 is an 8-bit register with readback capability  
designed to store data as well as read the register informa-  
tion back onto the data bus. The I/O bus (D bus) has 3-  
STATE outputs. Current sinking capability is 64 mA on both  
the D and Q busses.  
■ 3-STATE outputs on the I/O port  
■ D and Q output sink capability of 64 mA  
■ Functionally and pin equivalent to the 74LS794  
Data is loaded into the registers on the LOW-to-HIGH tran-  
sition of the clock (CP). The output enable (OE) is used to  
enable data on D0–D7. When OE is LOW, the output of the  
registers is enabled on D0–D7, enabling D as an output  
bus. When OE is HIGH, D0–D7 are inputs to the registers  
configuring D as an input bus.  
Ordering Code:  
Order Number  
74F794SC  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
74F794PC  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
© 1999 Fairchild Semiconductor Corporation  
DS010652  
www.fairchildsemi.com  
Input Loading/Fan-Out  
HIGH/LOW  
Current  
Pin Names  
Description  
(U.L.)  
Output Enable Input  
1.0/1.0  
20 µA/−0.6 mA  
OE  
CP  
Clock Pulse Inputs  
D Bus Inputs/  
1.0/1.0  
20 µA/−0.6 mA  
70 µA/−650 µA  
−15 mA/64 mA  
−15 mA/64 mA  
D0–D7  
3.5/1.083  
750/106.6  
750/106.6  
3-STATE Outputs  
Q Bus Outputs  
Q0–Q7  
Truth Table  
Logic Diagram  
Inputs  
CP  
Outputs  
OE  
L
Q
Qn  
Qn  
Qn  
D
D
L or H or ↓  
Output, Q  
L or H or ↓  
H
Input  
↑
↑
L
Output, Q (Note 1)  
Input  
H
Note 1: In this case the output of the register is clocked to the inputs and  
the overall Q output is unchanged at Q .  
n
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
−65°C to + 150°C  
Storage Temperature  
Ambient Temperature under Bias  
Junction Temperature under Bias  
−55° to +125°C  
−55°C to +150°C  
−0.5V to +7.0V  
−0.5V to +7.0V  
−30 mA to +5.0 mA  
4000V  
Free Air Ambient Temperature  
Supply Voltage  
0°C to 70°C  
+4.5V to +5.5V  
V
CC Pin Potential to Ground Pin  
Input Voltage (Note 3)  
Input Current (Note 3)  
ESD Last Passing Voltage (Min)  
Voltage Applied to Output  
In HIGH State (with VCC = 0V)  
Standard Output  
Note 2: Absolute maximum ratings are values beyond which the device  
may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
−0.5V to VCC  
3-STATE Output  
−0.5V to +5.5V  
Note 3: In this case the output of the register is clocked to the inputs and  
the overall Q output is unchanged at Q .  
n
Current Applied to Output  
in LOW State (Max)  
Note 4: Either voltage limit or current limit is sufficient to protect inputs.  
Twice the Rated IOL (mA)  
DC Electrical Characteristics over Operating Temperature Range unless otherwise specified  
V
Symbol  
Parameter  
Input HIGH Voltage  
Min  
Typ  
Max  
Units  
Conditions  
CC  
V
V
V
2.0  
V
V
Recognized as a HIGH Signal  
Recognized as a LOW Signal  
IH  
Input LOW Voltage  
Input Clamp  
Diode Voltage  
Output HIGH  
Voltage  
0.8  
IL  
CD  
−1.2  
V
V
Min  
Min  
Min  
Max  
I
= −18 mA  
IN  
V
2.4  
2.0  
2.8  
I
I
= −3 mA  
OH  
OL  
OH  
OH  
2.44  
= −15 mA  
V
Output LOW  
Voltage  
0.45  
0.55  
5.0  
V
I
= 64 mA  
= 2.7V  
OL  
I
Input HIGH  
Current  
IH  
µA  
V
IN  
I
Input HIGH Current  
Breakdown Test  
Input HIGH Current  
Breakdown (I/O)  
Output HIGH  
Leakage Current  
Input Leakage  
Test  
BVI  
7.0  
0.5  
50  
µA  
mA  
µA  
V
Max  
Max  
Max  
0.0  
V
V
V
= 7.0V (OE, CP)  
IN  
I
BVIT  
= 5.5V (D )  
IN  
n
I
CEX  
= V  
OUT  
CC  
V
I
= 1.9 µA  
ID  
ID  
4.75  
All Other Pins Grounded  
V = 150 mV  
IOD  
I
Output Leakage  
Circuit Current  
Input LOW  
OD  
3.75  
−0.6  
−225  
70  
µA  
mA  
mA  
µA  
µA  
V
0.0  
All Other Pins Grounded  
V = 0.5V  
IN  
I
IL  
Max  
Max  
Max  
Max  
0.0  
Current  
(OE, CP)  
I
Output Short-  
OS  
−100  
V
V
= 0V  
OUT  
Circuit Current  
I
+
Output Leakage Current  
= 2.7V  
IH  
OUT  
I
(Dn)  
OZH  
I
+
Output Leakage  
Current  
V
= 0.5V  
OUT  
IL  
−650  
I
(Dn)  
I = 1.9 µA  
ID  
OZL  
V
Input Leakage  
ID  
4.75  
Test  
All Other Pins Grounded  
V = 150 mV  
IOD  
I
Output Circuit  
OD  
3.75  
µA  
0.0  
Leakage Current  
Bus Drainage Test  
Power Supply Current  
Power Supply Current  
Power Supply Current  
All Other Pins Grounded  
I
100  
65  
µA  
mA  
mA  
mA  
0.0  
V
V
V
V
= 5.25V  
OUT  
ZZ  
I
Max  
Max  
Max  
= HIGH  
CCH  
O
O
O
I
80  
= LOW  
= HIGH Z  
CCL  
I
80  
CCZ  
3
www.fairchildsemi.com  
AC Electrical Characteristics  
T
= +25°C  
T = 0°C to +70°C  
A
A
V
= +5.0V  
= 50 pF  
Typ  
V
= +5.0V  
C = 50 pF  
L
CC  
CC  
Symbol  
Parameter  
Units  
C
L
Min  
90  
Max  
Min  
90  
Max  
f
Maximum Clock Frequency  
Propagation Delay  
CP to Q  
MHz  
ns  
MAX  
t
2.5  
2.5  
2.3  
2.0  
1.0  
1.0  
4.0  
4.0  
1.5  
1.5  
5.8  
5.8  
7.0  
8.0  
8.5  
10.0  
7.0  
7.0  
2.5  
2.5  
2.0  
2.0  
1.0  
1.0  
4.0  
4.0  
1.5  
1.5  
5.8  
5.8  
8.0  
9.0  
PLH  
t
PHL  
n
t
Output Enable Time  
9.0  
PZH  
ns  
ns  
ns  
ns  
ns  
t
10.5  
8.0  
PZL  
t
Output Disable Time  
PHZ  
t
8.0  
PLZ  
t (H)  
Setup Time, HIGH or LOW  
Bus to Clock  
S
t (L)  
S
t
(H)  
(L)  
Hold Time, HIGH or LOW  
Bus to Clock  
H
t
H
t
(H  
Clock Pulse Width  
HIGH or LOW  
W
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
Package Number M20B  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
6

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