74FR240SJ [FAIRCHILD]

Octal Buffer/Line Driver with 3-STATE Outputs; 八路缓冲器/ 3态输出线路驱动器


型号：	74FR240SJ
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Octal Buffer/Line Driver with 3-STATE Outputs 八路缓冲器/ 3态输出线路驱动器驱动器
文件：	总5页 (文件大小：54K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

October 1991

Revised August 1999

74FR240

Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The 74FR240 is an inverting octal buffer and line driver

designed to be employed as memory and address driver,

clock driver and bus oriented transmitter or receiver.

Features

■ 3-STATE outputs drive bus lines or buffer memory

address registers

■ Outputs sink 64 mA and source 15 mA

■ Guaranteed pin-to-pin skew

Ordering Code:

Order Number Package Number

Package Description

74FR240SC

74FR240SJ

74FR240PC

M20B

M20D

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Description

OE₁, OE₂

I₀–I₇

Output Enable Input (Active-LOW)

Inputs

O₀–O₇

Outputs

Truth Tables

Inputs

OE₁

Outputs

I_n

(Pins 12, 14, 16, 18)

Inputs

OE₂

Outputs

I_n

(Pins 3, 5, 7, 9)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

DS010901

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Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

Storage Temperature

−65°C to +150°C

Ambient Temperature under Bias

Junction Temperature under Bias

V_CCPin Potential to Ground Pin

Input Voltage (Note 2)

−55°C to +125°C

−55°C to +150°C

−0.5V to +7.0V

Free Air Ambient Temperature

Supply Voltage

0°C to +70°C

+4.5V to +5.5V

−0.5V to +7.0V

Input Current (Note 2)

−30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with V_CC= 0V)

Standard Output

−0.5V to V_CC

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

3-STATE Output

−0.5V to +5.5V

Current Applied to Output

in LOW State (Max)

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Twice the Rated I_OL(mA)

4000V

ESD Last Passing Voltage (Min)

DC Electrical Characteristics

Symbol

Parameter

Input HIGH Voltage

Min

Typ

Max

Units

Conditions

2.0

Recognized HIGH Signal

Recognized LOW Signal

Input LOW Voltage

0.8

Input Clamp Diode Voltage

Output HIGH Voltage

−1.2

Min

Max

= −18 mA

2.4

2.0

= −3 mA

= −15 mA

= 64 mA

= 2.7V

Output LOW Voltage

Input HIGH Current

Breakdown Test

0.55

µA

BVI

µA

Max

= 7.0V

= 0.5V

Input Low Current

Input Leakage Test

−150

µA

Max

0.0

4.75

= 1.9 µA,

All Other Pins Grounded

V = 150 mV,

IOD

Output Circuit Leakage Current

3.75

µA

0.0

All Other Pins Grounded

Output Leakage Current

Output Short-Circuit Current

Output HIGH Leakage Current

Bus Drainage Test

−20

−225

µA

Max

0.0

= 2.7V

= 0.5V

= 0.0V

OZH

OUT

OZL

−100

= V

CEX

100

= 5.25V

Power Supply Current

Input Capacitance

Max

5.0

All Outputs HIGH

All Outputs LOW

Outputs 3-STATE

CCH

8.0

CCL

CCZ

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AC Electrical Characteristics

= +25°C

T = 0°C to +70°C

= +5.0V

= 50 pF

= +5.0V

C = 50 pF

Symbol

Parameter

Units

Min

1.0

2.6

1.7

Typ

3.3

2.9

4.0

6.3

3.3

2.9

Max

4.7

7.0

6.6

Min

1.0

2.6

1.7

Max

Propagation Delay

to B or B to A

4.7

7.0

6.6

PLH

PHL

PZH

PZL

PHZ

PLZ

Output Enable Time

Output Disable Time

Extended AC Electrical Characteristics

= 0°C to +70°C

T = 0°C to +70°C

= +5.0V

= 50 pF

= +5.0V

= 250 pF

Symbol

Parameter

Units

Eight Outputs Switching

(Note 3)

(Note 4)

Min

1.0

2.6

1.7

Max

6.4

7.2

6.8

Min

2.3

Max

8.3

Propagation Delay

to B or B to A

PLH

8.3

PHL

PZH

PZL

Output Enable Time

Output Disable Time

PHZ

PLZ

Pin-to-Pin Skew

for HL Transitions

Pin-to-Pin Skew

for LH Transitions

Pin-to-Pin Skew

for HL/LH Transitions

OSHL

2.0

1.1

3.1

(Note 5)

OSLH

(Note 5)

OST

(Note 5)

Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,

i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.

Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load

capacitors in the standard AC load. This specification pertains to single output switching only.

Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-

cation applies to any outputs switching HIGH-to-LOW, (t

teed with all outputs switching in phase.

), LOW-to-HIGH, (t

), or HIGH-to-LOW and/or LOW-to-HIGH, (t

). Specifications guaran-

OST

OSHL

OSLH

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Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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