74LCX162374GX [FAIRCHILD]
Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26з Series Resistors; 低电压16位D型触发器具有5V容限输入和输出，并26з系列电阻器
| 型号： | 74LCX162374GX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26з Series Resistors |
| 文件： | 总10页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2001
Revised August 2001
74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
and 26Ω Series Resistors
General Description
Features
I 5V tolerant inputs and outputs
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
I 2.3V–3.6V VCC specifications provided
I Equivalent 26Ω series resistor on outputs
I 7.0 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Power down high impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
The LCX162374 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
I
12 mA output drive (VCC = 3.0V)
environment. The 26Ω series resistor in the output helps
reduce output overshoot and undershoot.
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Human body model > 2000V
Machine model > 200V
I Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX162374GX
(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LCX162374MEA
(Note 3)
MS48A
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162374MTD
(Note 3)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500442
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Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
Inputs
I0–I15
O0–O15
NC
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
CP1
NC
NC
I1
I0
I2
O4
O3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
I3
I4
O6
O5
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
I11
I13
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Pin Assignment for FBGA
Inputs
Outputs
CP1
OE1
I0–I7
O0–O7
L
L
H
L
H
L
L
L
X
X
O0
Z
X
H
Inputs
OE2
Outputs
O8–O15
CP2
I8–I15
L
L
H
L
H
L
(Top Thru View)
L
L
X
X
O0
Z
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of CP
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2
Functional Description
The LCX162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the con-
tents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 4)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
3-STATE
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 5)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
VO < GND
VO > VCC
mA
mA
IOK
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
mA
mA
mA
°C
ICC
100
IGND
TSTG
100
−65 to +150
Recommended Operating Conditions (Note 6)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
12
Units
VCC
Supply Voltage
Operating
V
V
V
Data Retention
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
VCC = 3.0V − 3.6V
VCC = 2.7V − 3.0V
VCC = 2.3V − 2.7V
8
mA
4
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
IOH = −100 µA
IOH = −4 mA
IOH = −4 mA
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOL = 100 µA
IOL = 4 mA
VCC − 0.2
1.8
2.7
2.2
V
V
3.0
2.4
2.7
2.0
3.0
2.0
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
0.4
0.55
0.6
0.8
5.0
IOL = 4 mA
2.7
IOL = 6 mA
3.0
IOL = 8 mA
2.7
IOL = 12 mA
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
3.0
II
Input Leakage Current
2.3 − 3.6
µA
µA
IOZ
3-STATE Output Leakage
2.3 − 3.6
5.0
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4
DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
IOFF
Parameter
Conditions
VI or VO = 5.5V
Units
µA
(V)
Min
Max
10
Power-Off Leakage Current
Quiescent Supply Current
0
ICC
VI = VCC or GND
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
20
µA
3.6V ≤ VI, VO ≤ 5.5V (Note 7)
VIH = VCC −0.6V
20
∆ICC
Increase in ICC per Input
500
µA
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = −40° to +85°C, RL = 500Ω
VCC = 3.3V 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V 0.2V
CL = 30 pF
Symbol
Parameter
Units
Min
170
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
Max
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
MHz
ns
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
Propagation Delay
CP to On
7.0
7.0
6.9
6.9
6.0
6.0
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
7.3
7.3
7.1
7.1
6.2
6.2
1.5
1.5
1.5
1.5
1.5
1.5
3.0
2.0
3.5
8.4
8.4
9.0
9.0
7.2
7.2
Output Enable time
ns
ns
Output Disable Time
Setup Time
ns
ns
ns
tH
Hold Time
tW
Pulse Width
tOSHL
tOSLH
Output to Output Skew (Note 8)
1.0
1.0
ns
Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.35
Quiet Output Dynamic Peak VOL
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.25
VOLV
Quiet Output Dynamic Valley VOL
−0.35
−0.25
Capacitance
Symbol
Parameter
Conditions
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
VCC = Open, VI = 0V or VCC
7
8
COUT
CPD
VCC = 3.3V, VI = 0V or VCC
pF
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
5
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AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 0.3V, and 2.7V
VCC x 2 at VCC = 2.5 0.2V
tPZH, tPHZ
GND
3-STATE Output High Enable and
Disable Times for Logic
Waveform for Inverting and Non-Inverting Functions
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
2.5V 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
VOL + 0.3V
VOH − 0.3V
VOL + 0.3V
VOH − 0.3V
VOL + 0.15V
VOH − 0.15V
Vy
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6
Schematic Diagram Generic for LCX Family
7
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
Preliminary
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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