74LCX373MTC_NL_技术文档

February 2008

74LCX373

Low Voltage Octal Transparent Latch

with 5V Tolerant Inputs and Outputs

Features

General Description

■ 5V tolerant inputs and outputs

The LCX373 consists of eight latches with 3-STATE

outputs for bus organized system applications. The

device is designed for low voltage applications with

capability of interfacing to a 5V signal environment.

■ 2.3V–3.6V V specifications provided

CC

■ 8.0ns t max. (V = 3.3V), 10µA I max.

PD

CC

■ Power down high impedance inputs and outputs

(1)

The LCX373 is fabricated with an advanced CMOS

technology to achieve high speed operation while main-

taining CMOS low power dissipation.

■ Supports live insertion/withdrawal

■ 24mA output drive (V = 3.0V)

CC

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds JEDEC 78 conditions

■ ESD performance

– Human body model > 2000V

– Machine model > 200V

■ Leadless DQFN package

Note:

1. To ensure the high impedance state during power up

or down, OE should be tied to V through a pull-up

CC

resistor: the minimum value of the resistor is

determined by the current-sourcing capability of the

driver.

Ordering Information

Order

Number

Package

Number

Package Description

74LCX373WM

74LCX373SJ

74LCX373BQX

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

(2)

MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 4.5mm

74LCX373MSA

74LCX373MTC

MSA20

MTC20

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Note:

2. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

Connection Diagrams

Logic Symbols

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

D₀D₁D₂D₃D₄D₅D₆D₇

LE

OE

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V_CC

O₇

D₇

D₆

O₆

O₅

D₅

D₄

O₄

OE

O₀

D₀

O₀O₁O₂O₃O₄O₅O₆O₇

D₁

O₁

O₂

D₂

IEEE/IEC

EN

OE

LE

C1

D₃

O₃

GND

D₀

D₁

D₂

D₃

D₄

D₅

D₆

D₇

1D

O₀

O₁

O₂

O₃

O₄

O₅

O₆

O₇

LE

Pad Assignments for DQFN

V_CC

OE

1

20

19

18

17

16

15

14

13

12

O₀

D₀

D₁

O₁

O₂

D₂

D₃

O₃

2

3

4

5

6

7

8

9

O₇

D₇

D₆

O₆

O₅

D₅

D₄

O₄

Truth Table

Inputs

Outputs

LE

X

OE

H

D

O

n

X

Z

L

H

L

H

X

H

L

H

10

11

L

O

0

GND LE

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immaterial

(Top View)

Pin Descriptions

Pin Names

Description

O = Previous O before HIGH-to-LOW transition

0

D –D

Data Inputs

Latch Enable Input

of Latch Enable

0

7

LE

OE

3-STATE Output Enable Input

3-STATE Latch Outputs

Functional Description

The LCX373 contains eight D-type latches with 3-STATE

standard outputs. When the Latch Enable (LE) input is

O –O

0

7

HIGH, data on the D inputs enters the latches. In this

n

condition the latches are transparent, i.e. a latch output

will change state each time its D input changes. When

LE is LOW, the latches store the information that was

present on the D inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE standard

outputs are controlled by the Output Enable (OE) input.

When OE is LOW, the standard outputs are in the

2-state mode. When OE is HIGH, the standard outputs

are in the high impedance mode but this does not inter-

fere with entering new data into the latches.

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

2

Logic Diagram

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

O

G

LE

OE

O

7

0

1

2

3

4

5

6

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Conditions

Value

Units

V

Supply Voltage

–0.5 to +7.0

V

CC

V

DC Input Voltage

I

V

DC Output Voltage

Output in 3-STATE

Output in HIGH or LOW State

V < GND

O

(3)

–0.5 to V + 0.5

CC

I

DC Input Diode Current

DC Output Diode Current

–50

mA

IK

I

V < GND

O

OK

V

> V

+50

O

CC

I

DC Output Source/Sink Current

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

±50

mA

°C

O

±100

CC

I

±100

GND

T

–65 to +150

STG

(4)

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Conditions

Min.

2.0

1.5

0

Max.

3.6

Units

V

Supply Voltage

Operating

V

CC

Data Retention

3.6

V

Input Voltage

5.5

V

I

V

Output Voltage

HIGH or LOW State

3-STATE

0

V

CC

O

0

5.5

±24

±12

±8

I

/I

Output Current

V

= 3.0V–3.6V

= 2.7V–3.0V

= 2.3V–2.7V

mA

OH OL

CC

T

Free-Air Operating Temperature

Input Edge Rate

–40

0

85

°C

A

∆t/∆V

V

= 0.8V–2.0V, V = 3.0V

10

ns/V

IN

CC

Notes:

3. I Absolute Maximum Rating must be observed.

O

4. Unused inputs must be held HIGH or LOW. They may not float.

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

4

DC Electrical Characteristics

T = –40°C to +85°C

A

Symbol

Parameter

V

(V)

Conditions

Min.

1.7

Max.

Units

CC

V

HIGH Level Input Voltage

2.3–2.7

2.7–3.6

2.3–2.7

2.7–3.6

2.3–3.6

2.3

V

IH

2.0

V

LOW Level Input Voltage

HIGH Level Output Voltage

0.7

0.8

V

IL

V

I

= –100µA

= –8mA

= –12mA

= –18mA

= –24mA

= 100µA

= 8mA

V

– 0.2

OH

OL

CC

1.8

2.2

2.4

2.2

2.7

3.0

V

LOW Level Output Voltage

2.3–3.6

2.3

0.2

0.6

V

OL

2.7

= 12mA

= 16mA

= 24mA

0.4

3.0

0.4

3.0

0.55

±5.0

I

Input Leakage Current

2.3–3.6 0 ≤ V ≤ 5.5V

µA

I

3-STATE Output Leakage

2.3–3.6 0 ≤ V ≤ 5.5V,

O

OZ

V = V or V

I

IH

IL

I

Power-Off Leakage Current

Quiescent Supply Current

0

V or V = 5.5V

10

µA

OFF

I

O

I

2.3–3.6 V = V or GND

I CC

CC

(5)

2.3–3.6 3.6V ≤ V , V ≤ 5.5V

±10

500

I

O

∆I

Increase in I per Input

2.3–3.6

V

= V –0.6V

µA

CC

IH

CC

AC Electrical Characteristics

T_A= –40°C to +85°C, R_L= 500Ω

V_CC= 3.3V ± 0.3V,

C_L= 50pF

V_CC= 2.7V,

C_L= 50pF

V_CC= 2.5 ± 0.2V,

C_L= 30pF

Symbol

Parameter

Propagation Delay, D to O

n

Min.

1.5

2.5

1.5

3.3

Max.

8.0

Min.

1.5

Max.

9.0

Min.

1.5

4.0

2.0

4.0

Max.

9.6

Units

ns

t

, t

PHL PLH

n

, t

Propagation Delay, LE to O

Output Enable Time

8.5

1.5

2.5

1.5

3.3

9.5

8.5

10.5

9.0

ns

PHL PLH

n

t

, t

8.5

ns

PZL PZH

, t

Output Disable Time

7.5

ns

PLZ PHZ

t

Setup Time, D to LE

ns

S

H

n

t

Hold Time, D to LE

ns

n

t

LE Pulse Width

ns

W

(6)

t

Output to Output Skew

1.0

ns

OSHL, OSLH

Notes:

5. Outputs disabled or 3-STATE only.

6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).

OSHL

OSLH

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

5

Dynamic Switching Characteristics

T = 25°C

A

Symbol

Parameter

V

(V)

Conditions

Typical

0.8

Units

CC

V

Quiet Output Dynamic Peak V

3.3

C = 50pF, V = 3.3V, V = 0V

V

OLP

OL

L

IH

IL

2.5

3.3

2.5

C = 30pF, V = 2.5V, V = 0V

0.6

L

I

IL

V

Quiet Output Dynamic Valley V

C = 50pF, V = 3.3V, V = 0V

–0.8

–0.6

V

OLV

OL

L

IH

IL

C = 30pF, V = 2.5V, V = 0V

L

I

IL

Capacitance

Symbol

Parameter

Conditions

Typical Units

C

Input Capacitance

Output Capacitance

Power Dissipation Capacitance

V

= Open, V = 0V or V

CC

7

8

pF

IN

CC

I

C

= 3.3V, V = 0V or V

I CC

OUT

C

= 3.3V, V = 0V or V , f = 10MHz

25

PD

I

CC

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

6

AC Loading and Waveforms (Generic for LCX Family)

V

CC

OPEN

GND

t

, t

PLH PHL

500Ω

TEST

, t

PZH PHZ

DUT

SIGNAL

V

, t

PZL PLZ

I

C

L

500Ω

Figure 1. AC Test Circuit (C includes probe and jig capacitance)

L

Test

Switch

t

, t

Open

PLH PHL

t

, t

6V at V = 3.3 ± 0.3V

CC

PZL PLZ

V

x 2 at V = 2.5 ± 0.2V

CC

t

, t

GND

PZH PHZ

V

CC

OUTPUT

CONTROL

DATA

IN

V

mi

V

mi

GND

t

PHZ

pxx

PZH

V

OH

Y

DATA

OUT

DATA

OUT

V

mo

3-STATE Output High Enable and

Disable Times for Logic

Waveform for Inverting and

Non-Inverting Functions

t

W

V

CC

DATA

V

CC

mi

CONTROL

IN

V

mi

GND

t

S

t

H

t

rec

V

CC

CONTROL

INPUT

V

mi

V

CLOCK

GND

mi

t

S

t

PHL

t

rec

t

PLH

MR

OR

CLEAR

V

mi

V

mo

OUTPUT

V

mo

Setup Time, Hold Time and

Recovery Time for Logic

Propagation Delay, Pulse Width and

Waveforms

t

rec

t

f

r

V

CC

OUTPUT

V

mi

CONTROL

GND

t

PLZ

PZL

V

OH

OL

90%

10%

ANY

OUTPUT

DATA

OUT

V

mo

V

X

10%

V

OL

t

and t

fall

rise

3-STATE Output Low Enable and

Disable Times for Logic

Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)

r

f

V

CC

Symbol

3.3V ± 0.3V

1.5V

2.7V

1.5V

2.5V ± 0.2V

V

/ 2

mi

CC

V

1.5V

mo

V

+ 0.3V

– 0.3V

V

+ 0.3V

V

+ 0.15V

– 0.15V

x

y

OL

V

– 0.3V

V

OH

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

7

Schematic Diagram (Generic for LCX Family)

Input Stage

P2

P1

V

CC

Data

ESD

P5

X1

D2 N+/P–

V

DD

N1

N2

P4

GTO™

Output

Input Stage

D6

N+/P–

P3

N5

Enable

N4

ESD

D4 N+/P–

N3

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

8

Tape and Reel Specification

Tape Format for DQFN

Package

Designator

Tape

Section

Number

Cavities

Cavity

Status

Cover Tape

Status

BQX

Leader (Start End)

Carrier

125 (typ)

3000

Empty

Filled

Sealed

Trailer (Hub End)

75 (typ)

Empty

Tape Dimensions inches (millimeters)

Reel Dimensions inches (millimeters)

Tape Size

A

B

C

D

N

W1

W2

12mm

13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

9

Physical Dimensions

13.00

12.60

A

11.43

20

11

B

9.50

10.65 7.60

10.00 7.40

2.25

1

PIN ONE

INDICATOR

10

0.65

0.51

0.35

1.27

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

2.65 MAX

0.33

0.20

C

0.10

C

0.30

0.10

SEATING PLANE

0.75

0.25

X 45°

NOTES: UNLESS OTHERWISE SPECIFIED

(R0.10)

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

GAGE PLANE

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

0.25

8°

0°

D) CONFORMS TO ASME Y14.5M-1994

1.27

0.40

SEATING PLANE

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

F) DRAWING FILENAME: MKT-M20BREV3

(1.40)

DETAIL A

SCALE: 2:1

Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

10

Physical Dimensions (Continued)

Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

11

Physical Dimensions (Continued)

Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

12

Physical Dimensions (Continued)

Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

13

Physical Dimensions (Continued)

Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

14

TRADEMARKS

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx^®

PDP-SPM™

SupreMOS™

FPS™

Power220^®

SyncFET™

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK^®

EZSWITCH™ *

™

FRFET^®

POWEREDGE^®

Power-SPM™

PowerTrench^®

Programmable Active Droop™

QFET^®

®

Global Power Resource^SM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

The Power Franchise^®

TinyBoost™

TinyBuck™

TinyLogic^®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC^®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM^®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

®

Fairchild^®

Fairchild Semiconductor^®

FACT Quiet Series™

FACT^®

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC^®

FAST^®

Ultra FRFET™

UniFET™

VCX™

OPTOPLANAR^®

FastvCore™

®

FlashWriter^{® *}

* EZSWITCH™ and FlashWriter^®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Advance Information

Formative or In Design

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

Preliminary

First Production

Full Production

Not In Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

No Identification Needed

Obsolete

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

74LCX373 Rev. 1.8.0

www.fairchildsemi.com

15


型号：	74LCX373MTC_NL
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, LEAD FREE, MO-153AC, TSSOP-20 驱动光电二极管逻辑集成电路
文件：	总15页 (文件大小：638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LCX373MTC_NL [FAIRCHILD]

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