74LCX760MSAX [FAIRCHILD]
BUFFER/DRIVER|DUAL|4-BIT|LCX-CMOS|SSOP|20PIN|PLASTIC ;
| 型号： | 74LCX760MSAX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | BUFFER/DRIVER|DUAL|4-BIT|LCX-CMOS|SSOP|20PIN|PLASTIC 逻辑集成电路 光电二极管 驱动 |
| 文件： | 总10页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2001
Revised February 2002
74LCX760
Low Voltage Buffer/Line Driver
with 5V Tolerant Inputs and Open Drain Outputs
General Description
Features
■ Open drain version of the LCX244
The LCX760 is the Open Drain version of the LCX244. The
LCX760 contains eight non-inverting buffers with 3-STATE
outputs. The device may be employed as a memory
address driver, clock driver and bus-oriented transmitter/
receiver. The LCX760 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V VCC specifications provided
■ 8.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ 24 mA output drive (VCC = 3.0V)
signal environment.
The LCX760 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ Implements patented noise/EMI reduction circuitry
■ Latch-up conforms to JEDEC JED78
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX760WM
74LCX760SJ
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 4.4mm Wide
74LCX760MSA
74LCX760MTC
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2002 Fairchild Semiconductor Corporation
DS500413
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Pin Descriptions
Truth Tables
Pin Names
OE1, OE2
Description
3-STATE Output Enable Inputs
I0–I7
Inputs
O0–O7
Outputs
Inputs
Inputs
Outputs
OE1
In
(Pins 12, 14, 16, 18)
L
L
L
H
X
L
H
Z
H
Outputs
OE2
In
(Pins 3, 5, 7, 9)
L
L
L
H
X
L
H
Z
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Absolute Maximum Ratings(Note 2)
Symbol
VCC
VI
Parameter
Supply Voltage
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
DC Input Voltage
V
VO
DC Output Voltage
Output in HIGH or LOW State (Note 3)
V
IIK
DC Input Diode Current
DC Output Diode Current
VI < GND
mA
IOK
−50
V
V
O < GND
O > VCC
mA
+50
IO
DC Output Sink Current
50
mA
mA
mA
°C
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 4)
Symbol
VCC
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
5.5
24
Units
Supply Voltage
Operating
V
Data Retention
VI
Input Voltage
Output Voltage
Output Current
V
V
VO
IOL
0
V
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
CC = 2.3V − 2.7V
12
mA
8
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs or I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
LOW Level Output Voltage
0.7
0.8
VOL
I
I
I
I
I
OL = 100 µA
OL = 8 mA
0.2
0.6
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
0.4
V
3.0
0.4
3.0
0.55
±5.0
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.3 − 3.6
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
2.3 − 3.6
±5.0
IOFF
ICC
Power-Off Leakage Current
Quiescent Supply Current
VI or VO = 5.5V
0
10
10
VI = VCC or GND
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
2 - 3.6
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
±10
500
10
∆ICC
Increase in ICC per Input
Off State Current
V
IH = VCC −0.6V
O = 5.5
µA
µA
IOHZ
V
Note 5: Outputs disabled or 3-STATE only.
3
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AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
VCC = 2.7V
V
CC = 3.3V ± 0.3V
VCC = 2.5V ± 0.2
L = 30 pF
Min Max
Symbol
Parameter
Units
CL= 50 pF
C
L = 50 pF
Max
C
Min
Max
8.0
Min
tPZL
tPLZ
tPZL
Propagation Delay
0.5
0.5
0.5
0.5
9.0
8.0
0.5
0.5
10.0
8.4
ns
ns
ns
ns
Data to Output
Output Enable Time
OEn to Out
7.0
0.5
0.5
8.0
7.0
0.5
0.5
9.0
8.0
0.5
0.5
10.0
8.4
tPLZ
Output Disable Time
OEn to Out
tOSHL
tOSLH
Output to Output Skew
(Note 6)
1.0
1.0
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
V
V
V
7
8
COUT
CPD
CC = 3.3V, VI = 0V or VCC
pF
Power Dissipation Capacitance
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
10
pF
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4
AC LOADING and WAVEFORMS
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
Vy
V
OH − 0.3V
V
OH − 0.3V
VOH − 0.15V
5
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Schematic Diagram Generic for LCX Family (output pull-up circuitry is not applicable to open drain versions)
FIGURE 3.
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 4.4mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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