74LCXZ16245MTD [FAIRCHILD]
Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs; 低电压16位双向收发器，具有5V容限输入和输出
| 型号： | 74LCXZ16245MTD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2002
Revised March 2002
74LCXZ16245
Low Voltage 16-Bit Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCXZ16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is designed for low volt-
age (2.7V or 3.3V) VCC applications with capability of inter-
■ 2.7V–3.6V VCC specifications provided
■ 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ ±24 mA output drive (VCC = 3.0V)
facing to a 5V signal environment. The device is byte
controlled. Each byte has separate control inputs which
could be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance conforms to the requirements of
JESD78
When VCC is between 0V and 1.5V, the LCXZ16245 is on
■ ESD performance:
the high impedance state during power-up or power-down.
This places the outputs in the high impedance (Z) state
preventing intermittent low impedance loading or glitching
in bus oriented applications.
Human body model > 2000V
Machine model > 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
The LCXZ16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
Package Description
74LCXZ16245GX
(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LCXZ16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 2: BGA package available in Tape and Reel only.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500580
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Connection Diagrams
Pin Descriptions
Pin Names
Description
Output Enable Input
Transmit/Receive Input
Pin Assignment for SSOP and TSSOP
OEn
T/Rn
A0–A15
B0–B15
NC
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
H
E
F
B0
B2
NC
B1
T/R1
NC
OE1
NC
NC
A1
A0
A2
B4
B3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
A3
A4
B6
B5
A5
A6
B8
B7
A7
A8
B10
B12
B14
B9
A9
A10
A12
A14
G
H
B11
B13
A11
A13
J
B15
NC
T/R2
OE2
NC
A15
Truth Tables
Inputs
Outputs
OE1
T/R1
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
H
Inputs
Outputs
Pin Assignment for FBGA
OE2
T/R2
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
H
HIGH Z State on A8–A15, B8–B15
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
(Top Thru View)
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2
Absolute Maximum Ratings(Note 3)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
mA
IOK
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 5)
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
VCC
5.5
±24
±12
85
Units
Supply Voltage
Input Voltage
Output Voltage
Operating
V
V
VI
VO
HIGH or LOW State
3-STATE
0
V
0
IOH/IOL
Output Current
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
mA
TA
Free-Air Operating Temperature
−40
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs or I/O's must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
Parameter
Conditions
Units
(V)
2.7 − 3.6
2.7 − 3.6
2.7 − 3.6
2.7
Min
Max
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
2.0
V
V
VIL
0.8
VOH
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 12 mA
OL = 16 mA
OL = 24 mA
VCC − 0.2
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.7 − 3.6
2.7
0.2
0.4
3.0
0.4
3.0
0.55
±5.0
±5.0
II
Input Leakage Current
3-STATE I/O Leakage
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.7 − 3.6
2.7 − 3.6
µA
µA
µA
µA
IOZ
IOFF
Power-Off Leakage Current
Power-Up/Power-Down
3-STATE Output Current
Quiescent Supply Current
VI or VO = 5.5V
O = 0.5V to VCC
0
10
IPU/PD
V
0 - 1.5
±5.0
VI = VCC or GND
ICC
VI = VCC or GND
2.7–3.6
2.7–3.6
2.7–3.6
225
±225
500
µA
µA
3.6V ≤ VI, VO ≤ 5.5V (Note 6)
∆ICC
Increase in ICC per Input
VIH = VCC −0.6V
Note 6: Outputs disabled or 3-STATE only.
3
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AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
CC = 3.3V ± 0.3V CC = 2.7V
L = 50 pF L = 50 pF
V
V
Symbol
Parameter
Units
C
C
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
4.5
4.5
6.5
6.5
6.4
6.4
1.0
1.0
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
5.2
5.2
7.2
7.2
6.9
6.9
tPHL
tPLH
tPZL
tPZH
tPLZ
Propagation Delay
ns
ns
ns
ns
An to Bn or Bn to An
Output Enable Time
Output Disable Time
tPHZ
tOSHL
tOSLH
Output to Output Skew (Note 7)
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
Parameter
Conditions
Units
(V)
3.3
3.3
Typical
0.8
VOLP
VOLV
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
V
V
C
−0.8
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
V
V
V
7
8
CI/O
CPD
CC = 3.3V, VI = 0V or VCC
pF
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 ± 0.3V, and 2.7V
tPZH, tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
Vmi
Vmo
Vx
1.5V
1.5V
V
OL + 0.3V
V
OL + 0.3V
Vy
V
OH − 0.3V
VOH − 0.3V
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
Preliminary
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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