74LVQ138SC [FAIRCHILD]
Low Voltage 1-of-8 Decoder/Demultiplexer; 低压1 - 8解码器/多路解复用器
| 型号： | 74LVQ138SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 1-of-8 Decoder/Demultiplexer |
| 文件： | 总8页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1998
74LVQ138
Low Voltage 1-of-8 Decoder/Demultiplexer
General Description
Features
n Ideal for low power/low noise 3.3V applications
The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables al-
low parallel expansion to a 1-of-24 decoder using just three
LVQ138 devices or a 1-of-32 decoder using four LVQ138 de-
vices and one inverter.
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
n Demultiplexing capability
n Multiple input enable for each expansion
n Active LOW mutually exclusive outputs
Ordering Code:
Order Number
74LVQ138SC
74LVQ138SJ
Package Number
M16A
Package Description
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
16-Lead Molded Small Outline Package, SOIC EIAJ
M16D
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for SOIC JEDEC and EIAJ
DS011350-1
IEEE/IEC
DS011350-2
Pin Descriptions
Pin Names
Description
Address Inputs
A0–A2
E1–E2
E3
Enable Inputs
Enable Input
Outputs
DS011350-4
O0–O7
© 1998 Fairchild Semiconductor Corporation
DS011350
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Functional Description
The LVQ138 high-speed 1-of-8 decoder/demultiplexer ac-
cepts three binary weighted inputs (A0, A1, A2) and, when
enabled, provides eight mutually exclusive active-LOW out-
puts (O0–O7). The LVQ138 features three Enable inputs, two
active-LOW (E1, E2) and one active-HIGH (E3). All outputs
will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion
of the device to a 1-of-32 (5 lines to 32 lines) decoder with
just four LVQ138 devices and one inverter (see Figure 1).
The LVQ138 can be used as an 8-output demultiplexer by
using one of the active LOW Enable inputs as the data input
and the other Enable inputs as strobes. The Enable inputs
which are not used must be permanently tied to their appro-
priate active-HIGH or active-LOW state.
Truth Table
Inputs
Outputs
E1
H
X
E2
X
E3
X
A0
X
A1
X
A2
X
O0
H
O1
H
O2
H
O3
H
O4
H
O5
H
O6
H
O7
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
Logic Diagram
DS011350-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Logic Diagram
3
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Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
)
Supply Voltage (VCC
)
2.0V to 3.6V
0V to VCC
=
VI −0.5V
−20 mA
+20 mA
Input Voltage (VI)
=
VI VCC + 0.5V
Output Voltage (VO
)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
−40˚C to +85˚C
DC Output Diode Current (IOK
)
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
@
VCC 3.0V
125 mV/ns
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for ac-
tual device operation.
±
50 mA
or Sink Current (IO
DC VCC or Ground Current
(ICC or IGND
)
±
)
200 mA
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
−65˚C to +150˚C
±
300 mA
DC Electrical Characteristics
VCC
=
=
Symbol
Parameter
TA +25˚C
TA −40˚C to +85˚C
Units
Conditions
(V)
3.0
3.0
Typ
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
1.5
1.5
2.0
0.8
2.0
0.8
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High Level
Output Voltage
3.0
3.0
2.99
2.9
2.9
V
V
=
VIN VIL or VIH (Note 3)
2.58
2.48
=
IOH −12 mA
=
IOUT 50 µA
VOL
Maximum Low Level
Outut Voltage
3.0
3.0
0.002
0.1
0.1
V
V
=
VIN VIL or VIH (Note 3)
0.36
0.44
=
IOL 12 mA
=
±
±
1.0
IIN
Maximum Input
3.6
0.1
µA
VI VCC, GND
Leakage Current
=
VOLD 0.8V Max (Note 5)
IOLD
IOH
ICC
Minimum Dynamic (Note 4)
Output Current
3.6
3.6
3.6
36
mA
mA
µA
=
VOHD 2.0V Min (Note 5)
−25
40.0
=
Maximum Quiescent
Supply Current
4.0
VIN VCC
or GND
VOLP
VOLV
VIHD
VILD
Quiet Output
3.3
3.3
3.3
3.3
0.8
−0.8
2.0
V
V
V
V
(Notes 6, 7)
Maximum Dynamic VOL
Quiet Output
(Notes 6, 7)
(Notes 6, 8)
(Notes 6, 8)
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
1.7
1.7
0.8
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V ), 0V to threshold
ILD
=
(V ), f 1 MHz.
IHD
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4
AC Electrical Characteristics
=
=
TA −40˚C to +85˚C
VCC
(V)
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Typ
10.2
8.5
Max
18.3
13.0
17.6
12.5
21.0
15.0
19.0
13.5
21.8
15.5
18.3
13.0
1.5
Min
Max
21.0
15.0
20.0
14.0
23.0
16.0
21.0
15.0
23.5
16.5
20.0
14.0
1.5
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Propagation Delay
2.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
±
An to On
3.3 0.3
Propagation Delay
An to On
2.7
9.6
±
3.3 0.3
8.0
Propagation Delay
E1 or E2 to On
Propagation Delay
E1 or E2 to On
Propagation Delay
E3 to On
2.7
13.2
11.0
11.4
9.5
±
3.3 0.3
2.7
±
3.3 0.3
2.7
13.2
11.0
10.2
8.5
±
3.3 0.3
Propagation Delay
E3 to On
2.7
±
3.3 0.3
tOSHL,
tOSLH
Output to Output Skew (Note 9)
Data to Output
2.7
1.0
±
3.3 0.3
1.0
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
) or LOW to HIGH (t ). Parameter guaranteed by design.
OSLH
OSHL
Capacitance
Symbol
Parameter
Input Capacitance
Typ
4.5
45
Units
Conditions
=
VCC Open
CIN
CPD (Note 10)
pF
pF
=
VCC 3.3V
Power Dissipation
Capacitance
Note 10:
C
PD
is measured at 10 MHz.
5
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead (0.150" Wide) Small Outline Integrated Circuit
Package Number M16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Molded Small Outline Package
Package Number M16D
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