74LVQ241QSC [FAIRCHILD]

Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs; 低压带3态输出的八路缓冲器/线路驱动器


型号：	74LVQ241QSC
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs 低压带3态输出的八路缓冲器/线路驱动器总线驱动器总线收发器逻辑集成电路光电二极管输出元件
文件：	总6页 (文件大小：65K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

February 1992

Revised June 2001

74LVQ241

Low Voltage Octal Buffer/Line Driver

with 3-STATE Outputs

General Description

Features

■ Ideal for low power/low noise 3.3V applications

The LVQ241 is an octal buffer and line driver designed to

be employed as a memory address driver, clock driver and

bus oriented transmitter or receiver which provides

improved PC board density.

■ Implements patented EMI reduction circuitry

■ Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-

ages

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Improved latch-up immunity

■ Guaranteed incident wave switching into 75Ω

■ 4 kV minimum ESD immunity

Ordering Code:

Order Number

74LVQ241SC

74LVQ241SJ

Package Number

M20B

Package Description

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

M20D

74LVQ241QSC

MQA20

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Diagram

Connection Diagram

IEEE/IEC

Truth Tables

Inputs

OE₁

Outputs

I_n

(Pins 12, 14, 16, 18)

Pin Descriptions

Pin Names

Description

OE₁, OE₂

I₀–I₇

3-STATE Output Enable Inputs

Inputs

OE₂

Outputs

Inputs

I_n

(Pins 3, 5, 7, 9)

O₀–O₇

Outputs

H = HIGH Voltage Level X = Immaterial

L = LOW Voltage Level Z = High Impedance

DS011355

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Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions ^{(Note 2)}

Supply Voltage (V_CC

)

−0.5V to +7.0V

DC Input Diode Current (I_IK

V_I= −0.5V

)

Supply Voltage (V_CC

)

2.0V to 3.6V

0V to V_CC

−20 mA

+20 mA

Input Voltage (V_I)

V_I= V_CC+ 0.5V

Output Voltage (V_O)

0V to V_CC

DC Input Voltage (V_I)

−0.5V to V_CC+ 0.5V

Operating Temperature (T_A)

−40°C to +85°C

DC Output Diode Current (I_OK

)

Minimum Input Edge Rate ∆V/∆t

_O= −0.5V

−20 mA

+20 mA

_IN0.8V to 2.0V

_O= V_CC+ 0.5V

V_CC@ 3.0V

125 mV/ns

DC Output Voltage (V_O)

DC Output Source

−0.5V to V_CC+ 0.5V

Note 1: The “Absolute Maximum Ratings” are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rat-

ings.The “Recommended Operating Conditions” table will define the condi-

tions for actual device operation

or Sink Current (I_O)

±50 mA

DC V_CCor Ground Current

(I_CCor I_GND

)

±400 mA

Note 2: Unused inputs must be held HIGH or LOW. They may not float.

Storage Temperature (T_STG

DC Latch-Up Source or

Sink Current

)

−65°C to +150°C

±300 mA

DC Electrical Characteristics

V_CC

_A= +25°C

T_A= −40°C to +85°C

Symbol

V_IH

Parameter

Units

Conditions

(V)

Typ

Guaranteed Limits

Minimum High Level

Input Voltage

_OUT= 0.1V

or V_CC− 0.1V

_OUT= 0.1V

or V_CC− 0.1V

_OUT= −50 µA

_IN= V_ILor V_IH(Note 3)

_OH= −12 mA

_OUT= 50 µA

_IN= V_ILor V_IH(Note 3)

_OL= 12 mA

3.0

1.5

2.0

V_IL

Maximum Low Level

Input Voltage

3.0

1.5

0.8

2.9

0.8

2.9

V_OH

Minimum High Level

Output Voltage

2.99

2.58

0.1

2.48

0.1

V_OL

Maximum Low Level

Output Voltage

0.002

0.36

0.44

I_IN

Maximum Input

V_I= V_CC,

3.6

±0.1

±1.0

µA

Leakage Current

Minimum Dynamic

Output Current (Note 4)

Maximum Quiescent

Supply Current

GND

I_OLD

I_OHD

I_CC

3.6

_OLD= 0.8V Max (Note 5)

−25

_OHD= 2.0V Min (Note 5)

_IN= V_CC

3.6

4.0

40.0

µA

or GND

I_OZ

Maximum 3-STATE

Leakage Current

V_I(OE) = V_IL, V_IH

V_I= V_CC, GND

3.6

±0.25

±2.5

µA

V_O= V_CC, GND

V_OLP

V_OLV

V_IHD

V_ILD

Quiet Output

3.3

0.4

−0.4

1.6

0.8

−0.8

2.0

(Note 6)(Note 7)

(Note 6)(Note 8)

Maximum Dynamic V_OL

Quiet Output

Minimum Dynamic V_OL

Maximum High Level

Dynamic Input Voltage

Maximum Low Level

Dynamic Input Voltage

1.6

0.8

Note 3: All outputs loaded; thresholds on input associated with output under test.

Note 4: Maximum test duration 2.0 ms, one output loaded at a time.

Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.

Note 6: Worst case package.

Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V. One output @ GND.

Note 8: Max number of Data Inputs (n) switching. n−1 Inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V_ILD), 0V to threshold

(V_IHD), f = 1 MHz.

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AC Electrical Characteristics

_A= +25°C

_A= −40°C to +85°C

_L= 50 pF

Max

Symbol

Parameter

V_CC

_L= 50 pF

Units

(V)

2.7

Min

2.0

2.5

1.0

Typ

7.8

6.5

9.6

8.0

10.2

8.5

1.0

Max

12.7

9.0

Min

t_PHL

t_PLH

t_PZL

Propagation Delay

2.0

2.5

1.0

14.0

9.5

Data to Output

3.3 ± 0.3

2.7

Output Enable Time

18.3

13.0

20.4

14.5

1.5

19.0

13.5

21.0

15.0

1.5

t_PZH

t_PHZ

t_PLZ

3.3 ± 0.3

2.7

Output Disable Time

3.3 ± 0.3

2.7

t_OSHL

t_OSLH

Output to Output

Skew Data to Output (Note 9)

3.3 ± 0.3

1.5

Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH). Parameter guaranteed by design.

Capacitance

Symbol

Parameter

Input Capacitance

Power Dissipation Capacitance

Note 10: C_PDis measured at 10 MHz.

Typ

4.5

Units

Conditions

C_IN

C_PD(Note 10)

_CC= Open

_CC= 3.3V

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Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Package Number MQA20

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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