74LVTH162373MEX [FAIRCHILD]
Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs; 低电压16位透明锁存器带3态输出和25з系列电阻的输出
| 型号： | 74LVTH162373MEX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 文件： | 总7页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2000
Revised November 2000
74LVTH162373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs and
25Ω Series Resistors in the Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVTH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
The LVTH162373 is designed with equivalent 25Ω series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
■ Functionally compatible with the 74 series 16373
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LVTH162373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
Human-body model > 2000V
Machine model > 200V
These latches are designed for low-voltage (3.3V) VCC
Charged-device model > 1000V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162373 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Ordering Code:
Package
Order Number
Package Description
Number
74LVTH162373MEA
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TUBES]
74LVTH162373MEX
(Note 1)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TAPE and REEL]
74LVTH162373MTD
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LVTH162373MTX
(Note 1)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
DS500354
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
LEn
I0–I15
O0–O15
3-STATE Outputs
Truth Tables
Inputs
Outputs
O0–O7
LE1
OE1
I0–I7
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
Oo
Inputs
OE2
Outputs
O8–O15
LE2
I8–I15
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
Oo
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
Oo = Previous output prior to HIGH-to-LOW transition of LE
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each
byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation.
The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the
latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes.
When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW
transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the
standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but
this does not interfere with entering new data into the latches.
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2
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 3)
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
VI < GND
mA
mA
−50
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
−12
12
Units
Supply Voltage
Input Voltage
V
V
VI
IOH
IOL
TA
HIGH Level Output Current
mA
mA
°C
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
−40
85
∆t/∆V
0
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
VCC
T
A = −40°C to +85°C
Symbol
Parameter
Units
Conditions
II = −18 mA
(V)
2.7
Min
Max
VIK
Input Clamp Diode Voltage
−1.2
V
V
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.0
V
V
O ≤ 0.1V or
O ≥ VCC − 0.1V
0.8
VOH
V
CC − 0.2
I
I
I
I
OH = −100 µA
OH = −12mA
OL = 100 µA
OL = 12 mA
V
V
2.0
VOL
Output LOW Voltage
2.7
0.2
0.8
3.0
II(HOLD)
II(OD)
II
Bushold Input Minimum Drive
3.0
75
−75
500
−500
VI = 0.8V
µA
µA
VI = 2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
3.0
(Note 4)
(Note 5)
3.6
3.6
10
±1
VI = 5.5V
Control Pins
Data Pins
VI = 0V or VCC
VI = 0V
µA
−5
3.6
0
1
VI = VCC
IOFF
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
±100
µA
µA
0V ≤ VI or VO ≤ 5.5V
IPU/PD
V
O = 0.5V to 3.0V
0–1.5V
±100
VI = GND or VCC
IOZL
IOZH
IOZH
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
−5
5
µA
µA
V
V
V
O = 0.5V
O = 3.0V
+
10
µA
CC < VO ≤ 5.5V
ICCH
ICCL
ICCZ
0.19
5
mA
mA
mA
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
Outputs Disabled
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4
DC Electrical Characteristics (Continued)
VCC
T A = −40°C to +85°C
Symbol
ICCZ
Parameter
Power Supply Current
Units
Conditions
VCC ≤ VO ≤ 5.5V,
(V)
Min
Max
+
3.6
0.19
mA
Outputs Disabled
∆ICC
Increase in Power Supply Current
(Note 6)
One Input at VCC − 0.6V
Other Inputs at VCC or GND
3.6
0.2
mA
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 7)
VCC
T
A = 25°C
Conditions
Symbol
Parameter
Units
C
L = 50 pF, RL = 500Ω
(V)
3.3
3.3
Min
Typ
0.8
Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
V
V
(Note 8)
(Note 8)
−0.8
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A = −40°C to +85°C, CL= 50pF, RL= 500Ω
CC = 3.3V ± 0.3V VCC = 2.7V
Max Min
Symbol
Parameter
V
Units
Min
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
1.0
1.0
3.0
Max
5.3
5.1
5.1
5.8
6.0
6.6
5.0
5.7
tPHL
Propagation Delay
Dn to On
4.8
4.8
5.0
5.1
5.0
5.4
5.1
5.4
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
0.8
1.1
3.0
ns
ns
ns
ns
tPLH
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
Propagation Delay
LE to On
Output Enable Time
Output Disable Time
Setup Time, Dn to LE
Hold Time, Dn to LE
LE Pulse Width
ns
ns
ns
tH
tW
tOSHL
tOSLH
Output to Output Skew (Note 9)
1.0
1.0
1.0
1.0
ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
CC = OPEN, VI = 0V or VCC
CC = 3.0V, VO = 0V or VCC
Typical
Units
pF
CIN
V
V
4
8
COUT
pF
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS48A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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