74LVTH322245 [FAIRCHILD]
Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25з Series Resistors in A Port Outputs; 低电压32位收发器与3态输出和25з系列电阻在港口输出
| 型号： | 74LVTH322245 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25з Series Resistors in A Port Outputs |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2002
Revised May 2002
74LVT322245 • 74LVTH322245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs
and 25Ω Series Resistors in A Port Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT322245 and LVTH322245 contain thirty-two non-
inverting bidirectional buffers with 3-STATE outputs and are
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 32-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322245)
■ Also available without bushold feature (74LVT322245)
■ Live insertion/extraction permitted
■ Power Up/Power Down high impedance provides
glitch-free bus loading
The LVT322245 and LVTH322245 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
■ A Port outputs include equivalent series resistance of
25Ω making external termination resistors unnecessary
and reducing overshoot and undershoot
■ A Port outputs source/sink ±12 mA
B Port outputs source/sink −32 mA/+64 mA
■ ESD performance:
The LVTH322245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
Human-body model > 2000V
These non-inverting transceivers are designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
Machine model > 200V
Charged-device model > 1000V
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
vide
a
TTL interface to
a 5V environment. The
LVT322245 and LVTH322245 are fabricated with an
advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.
Ordering Code:
Order Number
Package Number
Package Description
74LVT322245G
(Note 1) (Note 2)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH322245G
(Note 1) (Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates TRAYS.
Note 2: Devices also available in TAPE and REEL. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500408
www.fairchildsemi.com
Connection Diagram
FBGA Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Transmit/Receive Input
T/Rn
A0–A31
B0–B31
Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs
Pin Assignments for FBGA
1
2
3
4
5
6
A
B
C
D
E
F
B1
B3
B0
B2
T/R1
GND
OE1
A0
A2
A1
A3
GND
B5
B4
VCC1 VCC1
A4
A5
B7
B6
GND
GND
GND
GND
A6
A7
B9
B8
A8
A9
B11
B13
B10
B12
VCC1 VCC1
A10
A12
A11
A13
G
GND
T/R2
GND
OE2
H
B14
B15
A15
A14
J
K
L
B17
B19
B21
B23
B25
B27
B29
B16
B18
B20
B22
B24
B26
B28
T/R3
GND
OE3
A16
A18
A20
A22
A24
A26
A28
A17
A19
A21
A23
A25
A27
A29
(Top Thru View)
GND
VCC2 VCC2
M
N
P
R
GND
GND
GND
GND
VCC2 VCC2
GND
T/R4
GND
OE4
T
B30
B31
A31
A30
Truth Tables
Inputs
Inputs
Outputs
Outputs
OE1
T/R1
OE3
T/R3
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH-Z State on A0–A7, B0–B7
L
L
L
H
X
Bus B16–B23 Data to Bus A16–A23
Bus A16–A23 Data to Bus B16–B23
HIGH-Z State on A16–A23, B16–B23
H
H
Inputs
Inputs
Outputs
Outputs
OE2
T/R2
OE4
T/R4
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH-Z State on A8–A15, B8–B15
L
L
L
H
X
Bus B24–B31 Data to Bus A24–A31
Bus A24–A31 Data to Bus B24–B31
HIGH-Z State on A24–A31, B24–B31
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Functional Description
The LVT322245 and LVTH322245 contain thirty-two non-inverting bidirectional buffers with 3-STATE outputs. The device is
byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together
to obtain 16-bit or full 32-bit operation.
Logic Diagrams
Byte 1
Byte 3
Byte 2
Byte 4
V
CC1 is associated with Bytes 1 and 2.
CC2 is associated with Bytes 3 and 4.
V
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 3)
Symbol
VCC
Parameter
Supply Voltage
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
V
VI
DC Input Voltage
Output Voltage
VO
Output in 3-STATE
V
Output in HIGH or LOW State (Note 4)
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
VI < GND
mA
mA
−50
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
Units
Supply Voltage
3.6
5.5
−32
−12
64
V
V
VI
Input Voltage
IOH
HIGH Level Output Current
B Port
A Port
B Port
A Port
mA
mA
IOL
LOW Level Output Current
12
TA
Free Air Operating Temperature
−40
+85
10
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
II = −18 mA
(V)
2.7
Min
Max
VIK
Input Clamp Diode Voltage
−1.2
V
V
V
V
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
3.0
2.0
V
V
O ≤ 0.1V or
O ≥ VCC − 0.1V
0.8
VOH
2.0
CC− 0.2
2.4
I
I
I
I
I
I
I
I
I
I
OH = −12 mA
OH = −100 µA
OH = −8 mA
OH = −32 mA
OL = 12 mA
OL = 100 µA
OL = 24 mA
OL = 16 mA
OL = 32 mA
OL = 64 mA
A Port
B Port
A Port
2.7–3.6
2.7
V
V
3.0
2.0
VOL
Output LOW Voltage
3.0
0.8
0.2
V
V
2.7
2.7
0.5
3.0
0.4
B Port
V
3.0
0.5
3.0
0.55
II(HOLD)
(Note 5)
II(OD)
Bushold Input Minimum Drive
75
−75
500
−500
VI = 0.8V
3.0
3.0
µA
µA
VI = 2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
(Note 6)
(Note 5)
II
(Note 7)
3.6
3.6
10
±1
VI = 5.5V
Control Pins
Data Pins
VI = 0V or VCC
VI = 0V
µA
µA
−5
3.6
0
1
VI = VCC
IOFF
Power Off Leakage Current
±100
0V ≤ VI or VO ≤ 5.5V
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4
DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
IPU/PD
Parameter
Units
Conditions
(V)
Min
Max
Power Up/Down
3-STATE Current
V
O = 0.5V to 3.0V
0–1.5V
±100
µA
VI = GND to VCC
IOZL
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
−5
−5
µA
µA
V
V
O = 0.5V
O = 0.0V
IOZL
(Note 5)
IOZH
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
5
5
µA
µA
V
V
O = 3.0V
O = 3.6V
IOZH
(Note 5)
IOZH
+
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
10
0.19
5
µA
mA
mA
mA
V
CC < VO ≤ 5.5V
ICCH
ICCL
ICCZ
VCC1 or VCC2
VCC1 or VCC2
VCC1 or VCC2
VCC1 or VCC2
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
Outputs Disabled
ICCZ+
Power Supply Current
VCC ≤ VO ≤ 5.5V,
3.6
3.6
0.19
0.2
mA
mA
Outputs Disabled
∆ICC
Increase in Power Supply Current
(Note 8)
One Input at VCC − 0.6V
Other Inputs at VCC or GND
VCC1 or VCC2
Note 5: Applies to bushold versions only (74LVTH322245).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 9)
VCC
T
A = 25°C
Conditions
Symbol
Parameter
Units
C
L = 50 pF RL = 500Ω
(V)
3.3
3.3
Min
Typ
0.8
Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
V
V
(Note 10)
(Note 10)
−0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A = −40°C to +85°C
C
L = 50 pF, RL = 500Ω
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
VCC = 2.7V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
Max
4.0
3.7
3.5
3.5
5.3
5.6
4.6
5.3
5.6
5.5
5.4
5.1
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
Max
tPLH
Propagation Delay Data to A Port Output
Propagation Delay Data to B Port Output
Output Enable Time for A Port Output
Output Enable Time for B Port Output
Output Disable Time for A Port Output
Output Disable Time for B Port Output
4.6
4.1
3.9
3.9
6.3
7.2
5.4
6.9
6.3
5.5
6.1
5.4
ns
ns
ns
ns
ns
ns
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
Capacitance (Note 11)
Symbol
Parameter
Conditions
Typical
Units
CIN
Input Capacitance
V
CC = 0V, VI = 0V or VCC
CC = 3.0V, VO = 0V or VCC
4
8
pF
pF
CI/O
Input/Output Capacitance
V
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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