74LVX161284AMTX [FAIRCHILD]
Low Voltage IEEE 161284 Translating Transceiver; 低压IEEE 161284翻译收发器![74LVX161284AMTX](http://pdffile.icpdf.com/pdf1/p00057/img/icpdf/74LVX161284A_298044_icpdf.jpg)
型号: | 74LVX161284AMTX |
厂家: | ![]() |
描述: | Low Voltage IEEE 161284 Translating Transceiver |
文件: | 总9页 (文件大小:96K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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June 1999
Revised June 2005
74LVX161284A
Low Voltage IEEE 161284 Translating Transceiver
General Description
Features
The LVX161284A contains eight bidirectional data buffers
■ Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
with the exception of output slew rate
and eleven control/status buffers to implement
a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard, with the exception of output slew rate,
and is intended to be used in an Extended Capabilities Port
mode (ECP). The pinout allows for easy connection from
the Peripheral (A-side) to the Host (cable side).
■ Translation capability allows outputs on the cable side to
interface with 5V signals
■ All inputs have hysteresis to provide noise margin
Outputs on the cable side can be configured to be either
open drain or high drive ( 14 mA) and are connected to a
separate power supply pin (VCC cable) to allow these out-
■ B and Y output resistance optimized to drive external
cable
■ B and Y outputs in high impedance mode during power
down
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCC cable supply to provide proper
■ Inputs and outputs on cable side have internal pull-up
resistors
■ Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
termination and pull-ups for open drain mode.
■ Replaces the function of two (2) 74ACT1284 devices
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Ordering Code
Package
Order Number
Package Description
Number
74LVX161284AMTD
74LVX161284AMTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Connection Diagram
Pin Descriptions
Pin Names
HD
Description
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
DIR
A1–A8
B1–B8
A9–A13
Y9–Y13
A14–A17
Inputs or Outputs
Inputs
Outputs
Outputs
C
14–C17
Inputs
PLHIN
PLH
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
HLHIN
HLH
© 2005 Fairchild Semiconductor Corporation
DS500204
www.fairchildsemi.com
Logic Symbol
Truth Table
Inputs
Outputs
DIR
HD
L
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C
14–C17 Data to A14–A17
PLH Open Drain Mode
L
H
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
H
H
H
A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
Note 1: Y –Y Open Drain Outputs
9
13
Note 2: B –B Open Drain Outputs
1
8
Logic Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Supply Voltage
VCC
0.5V to 4.6V
Supply Voltage
VCC—Cable
0.5V to 7.0V
VCC
3.0V to 3.6V
3.0V to 5.5V
0V to VCC
VCC—Cable Must Be VCC
Input Voltage (VI)—(Note 4)
A1–A13, PLHIN, DIR, HD
B1–B8, C14–C17, HLHIN
B1–B8, C14–C17, HLHIN
VCC—Cable
DC Input Voltage (VI)
Open Drain Voltage (VO)
Operating Temperature (TA)
0.5V to VCC 0.5V
0.5V to 5.5V (DC)
2.0V to 7.0V*
0V to 5.5V
40 C to 85 C
*40 ns Transient
Output Voltage (VO)
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
B1–B8, Y9–Y13, PLH
0.5V to VCC 0.5V
0.5V to 5.5V (DC)
2.0V to 7.0V*
*40 ns Transient
DC Output Current (IO)
A1–A8, HLH
25 mA
50 mA
84 mA
50 mA
B1–B8, Y9–Y13
PLH (Output LOW)
PLH (Output HIGH)
Input Diode Current (IIK)—(Note 4)
DIR, HD, A9–A13, PLH, HLH, C14–C17
20 mA
Output Diode Current (IOK
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
)
50 mA
50 mA
Note 3: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.
DC Continuous VCC or Ground Current
Storage Temperature
200 mA
65 C to 150 C
2000V
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
ESD (HBM) Last Passing Voltage
DC Electrical Characteristics
V
V
T
A
40 C to 85 C
CC
CC—Cable
(V)
Symbol
Parameter
Units
Conditions
(V)
Guaranteed Limits
V
V
Input Clamp
Diode Voltage
Minimum
IK
3.0
3.0
1.2
V
I
18 mA
i
A , B , PLH , DIR, HD
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.3
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
5.0
2.0
2.3
2.6
0.8
0.8
1.6
0.4
0.8
0.2
2.8
2.4
2.0
2.23
3.1
IH
n
n
IN
HIGH Level
Input Voltage
Maximum
C
V
V
V
n
HLH
IN
V
A , B , PLH , DIR, HD
IL
n
n
IN
LOW Level
Input Voltage
Minimum Input
Hysteresis
C
n
HLH
IN
V
A , B , PLH , DIR, HD
V
V
V
–V
T
n
n
IN
T
T
T
T
C
3.3
5.0
–V
–V
n
T
HLH
3.3
5.0
IN
T
V
Minimum HIGH
Level Output
Voltage
A , HLH
3.0
3.0
I
I
I
I
I
50 A
OH
n
OH
OH
OH
OH
OH
3.0
3.0
4 mA
B , Y
3.0
3.0
V
14 mA
14 mA
n
n
n
B , Y
n
3.0
4.5
PLH
3.15
3.15
500 A
3
www.fairchildsemi.com
DC Electrical Characteristics (Continued)
V
V
T
A
40 C to 85 C
CC
CC—Cable
Symbol
Parameter
A , HLH
Units
Conditions
50
(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
(V)
Guaranteed Limits
V
Maximum LOW
Level Output
Voltage
3.0
0.2
0.4
I
I
I
I
I
I
A
OL
n
OL
OL
OL
OL
OL
OL
3.0
4 mA
B , Y
3.0
0.8
14 mA
14 mA
84 mA
84 mA
n
n
V
B , Y
n
4.5
0.77
0.95
0.9
n
PLH
PLH
3.0
4.5
R
R
Maximum Output
Impedance
B –B , Y –Y
3.3
60
D
1
8
9
13
13
13,
13
(Note 5)(Note 7)
(Note 5)(Note 7)
5.0
55
Minimum Output
Impedance
B –B , Y –Y
3.3
30
1
8
9
5.0
35
Maximum Pull-Up
Resistance
B –B , Y –Y
3.3
1650
1650
1150
1150
P
1
8
9
C
–C
5.0
14
17
Minimum Pull-Up
Resistance
B –B , Y –Y
3.3
1
8
9
C
–C
5.0
14
17
I
I
Maximum Input
Current in
A –A , PLH
,
V
3.6V
IH
9
13
IN
I
3.6
3.6
1.0
HD, DIR, HLH
IN
A
A
HIGH State
C
C
–C
–C
3.6
3.6
3.6
5.5
50.0
100
V
V
3.6V
5.5V
14
14
17
17
I
I
Maximum Input
Current in
A –A , PLH
IN
,
IL
9
13
3.6
3.6
1.0
V
0.0V
I
HD, DIR, HLH
IN
LOW State
C
C
–C
–C
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
5.5
3.6
3.6
5.5
3.6
3.6
5.5
3.5
5.0
20
mA
mA
A
V
V
V
V
V
V
0.0V
0.0V
3.6V
3.6V
5.5V
0.0V
14
17
17
I
14
I
I
I
Maximum Output
Disable Current
(HIGH)
A –A
1
OZH
OZL
8
8
8
8
8
8
O
O
O
O
B –B
50
A
1
B –B
100
20
A
1
Maximum
A –A
A
1
Output Disable
Current (LOW)
Power Down
Output Leakage
Power Down
Input Leakage
PowerDown
B –B
3.5
5.0
mA
mA
1
B –B
1
I
I
I
I
I
B –B , Y –Y
,
OFF
1
8
9
13
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
100
100
250
250
A
A
A
V
V
5.5V
5.5V
O
I
PLH
OFF
C
–C , HLH
17
14
IN
OFF—ICC
OFF—ICC2
CC
(Note 6)
(Note 6)
Leakage to V
CC
Power Down Leakage
to V
A
CC—Cable
Maximum Supply
Current
3.6
3.6
3.6
5.5
45
70
mA
V
V
V
V
or GND
or GND
I
I
CC
CC
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD HIGH).
Note 6: Power-down leakage to V or V is tested by simultaneously forcing all pins on the cable-side (B –B , Y –Y , PLH, C –C and HLH )
IN
CC
CC—Cable
1
8
9
13
14
17
to 5.5V and measuring the resulting I or I
.
CC
CC—Cable
Note 7: This parameter is guaranteed but not tested, characterized only.
www.fairchildsemi.com
4
AC Electrical Characteristics
T
40 C to 85 C
A
V
3.0V–3.6V
CC
Figure
Number
Symbol
Parameter
Units
V
4.5V–5.5V
Max
CC—Cable
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A –A to B –B
8.5
8.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 8)
Figure 1
Figure 2
Figure 3
Figure 3
PHL
1
8
1
8
8
8
8
A –A to B –B
PLH
PHL
PLH
PHL
PLH
PHL
PLH
SKEW
PHL
PLH
PHL
PLH
PHZ
PLZ
PZH
PZL
PHZ
PLZ
pEN
1
8
1
B –B to A –A
14.0
14.0
8.5
1
8
1
B –B to A –A
1
8
1
A –A to Y –Y
9
13
9
13
13
A –A to Y –Y
8.5
9
13
9
C
–C to A –A
10.0
10.0
2.0
14
14
17
14
17
17
C
–C to A –A
17 14
LH-LH or HL-HL
PLH to PLH
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.5
IN
PLH to PLH
8.5
IN
HLH to HLH
10.0
12.0
10.0
10.0
10.0
10.0
13.0
10.0
IN
HLH to HLH
IN
Output Disable Time
DIR to A –A
ns
ns
ns
ns
ns
Figure 4
Figure 5
Figure 6
Figure 2
Figure 2
1
8
Output Enable Time
DIR to A –A
1
8
Output Disable Time
DIR to B –B
1
8
Output Enable Time
HD to B –B , Y –Y
13
1.0
8.0
1
8
9
t
Output Disable Time
HD to B –B , Y –Y
pDIS
1.0
12.0
1
8
9
13
Note 8: t
is measured for common edge output transitions and compares the measured propagation delay for a given path type:
SKEW
(i) A –A to B –B , A –A to Y –Y
13
1
8
1
8
9
13
9
(ii) B –B to A –A
8
1
8
1
(iii) C –C to A –A
17
14
17
14
Capacitance
Symbol
Parameter
Typ
3
Units
pF
Conditions
0.0V (HD, DIR, A –A , C –C , PLH and HLH )
IN
C
Input Capacitance
V
V
IN
CC
CC
9
13
14
17
IN
C
(Note 9)
I/O Pin Capacitance
5
pF
3.3V
I/O
Note 9: C is measured at frequency 1 MHz, per MIL-STD-883B, Method 3012
I/O
5
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AC Loading and Waveforms
Pulse Generator for all pulses: Rate 1.0 MHz; ZO 50 ; tf 2.5 ns, tr 2.5 ns.
FIGURE 1. Port A to B and A to Y Propagation Delay Waveforms
FIGURE 2. Port A to B and A to Y Output Waveforms
FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms
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6
AC Loading and Waveforms (Continued)
FIGURE 4. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8
FIGURE 5. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8
7
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AC Loading and Waveforms (Continued)
FIGURE 6. tPHZ and tPLZ Test Load and Waveforms,
DIR to B1–B8
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8
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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