74LVX161284MTDX_NL [FAIRCHILD]
Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48;
| 型号： | 74LVX161284MTDX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总11页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1999
Revised June 2005
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
Features
■ Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement
a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
■ Translation capability allows outputs on the cable side to
interface with 5V signals
■ All inputs have hysteresis to provide noise margin
■ B and Y output resistance optimized to drive external
cable
Outputs on the cable side can be configured to be either
open drain or high drive ( 14 mA) and are connected to a
separate power supply pin (VCC-cable) to allow these out-
■ B and Y outputs in high impedance mode during power
down
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCC-cable supply to provide proper
■ Inputs and outputs on cable side have internal pull-up
resistors
■ Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
■ Replaces the function of two (2) 74ACT1284 devices
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Ordering Code
Order Number
74LVX161284MEA
74LVX161284MTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
HD
Description
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
DIR
A1–A8
B1–B8
A9–A13
Y9–Y13
Inputs or Outputs
Inputs
Outputs
A
14–A17
Outputs
C14–C17
PLHIN
PLH
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
HLHIN
HLH
© 2005 Fairchild Semiconductor Corporation
DS500202
www.fairchildsemi.com
Logic Symbol
Truth Table
Inputs
Outputs
DIR
HD
L
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
L
H
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
H
H
H
A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
Note 1: Y –Y Open Drain Outputs
9
13
Note 2: B –B Open Drain Outputs
1
8
Logic Diagram
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2
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Supply Voltage
VCC
0.5V to 4.6V
Supply Voltage
VCC—Cable
0.5V to 7.0V
VCC
3.0V to 3.6V
3.0V to 5.5V
0V to VCC
VCC—Cable Must Be VCC
Input Voltage (VI)—(Note 4)
A1–A13, PLHIN, DIR, HD
B1–B8, C14–C17, HLHIN
B1–B8, C14–C17, HLHIN
VCC—Cable
DC Input Voltage (VI)
Open Drain Voltage (VO)
Operating Temperature (TA)
0.5V to VCC 0.5V
0.5V to 5.5V (DC)
2.0V to 7.0V*
0V to 5.5V
40 C to 85 C
*40 ns Transient
Output Voltage (VO)
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
B1–B8, Y9–Y13, PLH
0.5V to VCC 0.5V
0.5V to 5.5V (DC)
2.0V to 7.0V*
*40 ns Transient
DC Output Current (IO)
A1–A8, HLH
25 mA
50 mA
84 mA
50 mA
B1–B8, Y9–Y13
PLH (Output LOW)
PLH (Output HIGH)
Input Diode Current (IIK)—(Note 4)
DIR, HD, A9–A13, PLH, HLH, C14–C17
20 mA
Output Diode Current (IOK
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
)
50 mA
50 mA
Note 3: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Fairchild does not recom-
mend operation outside the databook specifications.
DC Continuous VCC or Ground
Current
200 mA
65 C to 150 C
2000V
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
Storage Temperature
ESD (HBM) Last Passing Voltage
DC Electrical Characteristics
T
0 C
T
40 C
A
A
V
(V)
V
CC
CC—Cable
(V)
Symbol
Parameter
Units
Conditions
to 70 C
to 85 C
Guaranteed Limits
V
Input Clamp
Diode Voltage
Minimum
3.0
3.0
1.2
1.2
V
I
18 mA
IK
i
V
A , B , PLH , DIR, HD
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.3
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
5.0
2.0
2.3
2.6
0.8
0.8
1.6
0.4
0.8
0.2
2.8
2.4
2.0
2.23
3.1
2.0
2.3
2.6
0.8
0.8
1.6
0.4
0.8
0.2
2.8
2.4
2.0
2.23
3.1
IH
n
n
IN
HIGH Level
Input Voltage
Maximum
C
V
V
V
n
HLH
IN
V
A , B , PLH , DIR, HD
IL
n
n
IN
LOW Level
Input Voltage
Minimum Input
Hysteresis
C
n
HLH
IN
V
A , B , PLH , DIR, HD
V
V
V
–V
–V
–V
T
n
n
IN
T
T
T
T
C
3.3
5.0
n
T
HLH
3.3
5.0
IN
T
V
Minimum HIGH
Level Output
Voltage
A , HLH
3.0
3.0
I
I
I
I
I
50 A
OH
n
OH
OH
OH
OH
OH
3.0
3.0
4 mA
B , Y
3.0
3.0
V
14 mA
14 mA
n
n
B , Y
n
3.0
4.5
n
PLH
3.15
3.15
500 A
3
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DC Electrical Characteristics (Continued)
T
0 C
T
40 C
A
A
V
(V)
V
CC—Cable
CC
Symbol
Parameter
Units
Conditions
to 70 C
to 85 C
(V)
Guaranteed Limits
V
Maximum LOW
Level Output
Voltage
A , HLH
3.0
3.0
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.6
3.0
3.0
3.0
4.5
3.0
4.5
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.6
0.2
0.4
0.2
0.4
I
I
I
I
I
I
50 A
OL
n
OL
OL
OL
OL
OL
OL
4 mA
B , Y
0.8
0.8
14 mA
14 mA
84 mA
84 mA
n
n
V
B , Y
n
0.77
0.85
0.8
0.77
0.95
0.9
n
PLH
PLH
R
Maximum Output
Impedance
B –B , Y –Y
60
60
D
1
8
9
13
13
13,
13
(Note 5)(Note 7)
(Note 5)(Note 7)
55
55
Minimum Output
Impedance
B –B , Y –Y
30
30
1
8
9
35
35
R
Maximum Pull-Up
Resistance
B –B , Y –Y
1650
1650
1150
1150
1.0
1650
1650
1150
1150
1.0
P
1
8
9
C
–C
14
17
Minimum Pull-Up
Resistance
B –B , Y –Y
1
8
9
C
–C
14
17
I
I
Maximum Input
Current in
A –A , PLH
,
V
3.6V
IH
9
13
IN
I
HD, DIR, HLH
IN
A
A
HIGH State
C
C
–C
–C
3.6
3.6
3.6
3.6
5.5
3.6
50.0
100
1.0
50.0
100
1.0
V
V
V
3.6V
5.5V
0.0V
14
14
17
17
I
I
I
Maximum Input
Current in
A –A , PLH
IN
,
IL
9
13
HD, DIR, HLH
IN
LOW State
C
C
–C
–C
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
5.5
3.6
3.6
5.5
3.6
3.6
5.5
3.5
5.0
20
3.5
5.0
20
mA
mA
A
V
V
V
V
V
V
0.0V
0.0V
3.6V
3.6V
5.5V
0.0V
14
14
17
17
I
I
I
I
Maximum Output
Disable Current
(HIGH)
A –A
1
OZH
OZL
8
8
8
8
8
8
O
O
O
O
B –B
50
50
A
1
B –B
100
20
100
20
A
1
Maximum
A –A
A
1
Output Disable
Current (LOW)
Power Down
Output Leakage
Power Down
Input Leakage
Power Down
B –B
3.5
5.0
3.5
5.0
mA
mA
1
B –B
1
I
I
I
I
I
B –B , Y –Y
,
OFF
1
8
9
13
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
100
100
250
250
100
100
250
250
A
A
A
A
V
V
5.5V
5.5V
O
PLH
OFF
C
–C , HLH
17
14
IN
I
OFF—ICC
OFF—ICC2
CC
(Note 6)
(Note 6)
Leakage to V
CC
Power Down Leakage
to V
CC—Cable
Maximum Supply
Current
3.6
3.6
3.6
5.5
45
70
45
70
mA
mA
V
V
V
V
or GND
or GND
I
CC
I
CC
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD HIGH).
Note 6: Power-down leakage to V or V is tested by simultaneously forcing all pins on the cable-side (B –B , Y –Y , PLH, C –C and HLH )
IN
CC
CC—Cable
1
8
9
13
14
17
to 5.5V and measuring the resulting I or I
.
CC
CC—Cable
Note 7: This parameter is guaranteed but not tested, characterized only.
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4
AC Electrical Characteristics
T
0 C to 70 C
T
40 C to 85 C
A
A
V
3.0V–3.6V
V
3.0V–3.6V
CC
CC
Figure
Number
Symbol
Parameter
Units
V
3.0V–5.5V
V
3.0V–5.5V
CC—Cable
CC—Cable
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
10.0
40.0
40.0
40.0
40.0
15.0
15.0
50.0
50.0
50.0
50.0
25.0
25.0
25.0
25.0
10.0
Min
Max
44.0
44.0
44.0
44.0
44.0
44.0
44.0
44.0
12.0
44.0
44.0
44.0
44.0
18.0
18.0
50.0
50.0
50.0
50.0
28.0
28.0
28.0
28.0
12.0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A –A to B –B
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 9)
Figure 1
Figure 2
Figure 3
Figure 3
PHL
1
8
1
8
8
8
8
A –A to B –B
PLH
PHL
PLH
PHL
PLH
PHL
PLH
SKEW
PHL
PLH
PHL
PLH
PHZ
PLZ
PZH
PZL
PHZ
PLZ
pEN
1
8
1
B –B to A –A
1
8
1
B –B to A –A
1
8
1
A –A to Y –Y
9
13
9
13
13
A –A to Y –Y
9
13
9
C
–C to A –A
17 14
14
14
17
C
–C to A –A
17 14
17
LH-LH or HL-HL
PLH to PLH
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
IN
PLH to PLH
IN
HLH to HLH
IN
HLH to HLH
IN
Output Disable Time
DIR to A –A
ns
ns
ns
ns
Figure 7
Figure 8
Figure 9
Figure 2
Figure 2
1
8
Output Enable Time
DIR to A –A
1
8
Output Disable Time
DIR to B –B
1
8
Output Enable Time
HD to B –B , Y –Y
13
1
8
9
t
t
Output Disable Time
HD to B –B , Y –Y
13
pDIS
ns
ns
1
8
9
–t
Output Enable-
Output Disable
pEN pDIS
t
t
t
Output Slew Rate
SLEW
PLH
B –B , Y –Y
0.05
0.05
0.40
0.40
120
120
0.05
0.05
0.40
0.40
120
120
V/ns
ns
Figure 5
Figure 4
Figure 6
(Note 10)
1
8
9
13
PHL
t , t
t
and t
RISE FALL
r
f
B –B (Note 8),
1
8
Y –Y (Note 8)
9
13
Note 8: Open Drain
Note 9: t is measured for common edge output transitions and compares the measured propagation delay for a given path type:
SKEW
(i) A –A to B –B , A –A to Y –Y
13
1
8
1
8
9
13
9
(ii) B –B to A –A
8
1
8
1
(iii) C –C to A –A
17
14
17
14
Note 10: This parameter is guaranteed but not tested, characterized only.
Capacitance
Symbol
Parameter
Input Capacitance
(Note 11) I/O Pin Capacitance
Typ
3
Units
pF
Conditions
0.0V (HD, DIR, A –A , C –C , PLH and HLH )
IN
C
C
V
V
IN
CC
CC
9
13
14
17
IN
5
pF
3.3V
I/O
Note 11: C is measured at frequency 1 MHz, per MIL-STD-883B, Method 3012
I/O
5
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AC Loading and Waveforms
Pulse Generator for all pulses: Rate 1.0 MHz; ZO 50 ; tf 2.5 ns, tr 2.5 ns.
FIGURE 1. Port A to B and A to Y Propagation Delay Waveforms
FIGURE 2. Port A to B and A to Y Output Waveforms
FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms
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6
AC Loading and Waveforms (Continued)
FIGURE 4. Port A to B and A to Y HL Slew Test Load and Waveforms
FIGURE 5. Port A to B and A to Y LH Slew Test Load and Waveforms
7
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AC Loading and Waveforms (Continued)
t
t
Output Rise Time, Open Drain
Output Fall Time, Open Drain
r
f
FIGURE 6. Ports A to B and A to Y Rise and Fall Test Load and Waveforms for Open Drain Outputs
FIGURE 7. tPHZ and tPLZ Test Load and Waveforms, DIR to A1–A8
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8
AC Loading and Waveforms (Continued)
FIGURE 8. tPZH and tPZL Test Load and Waveforms, DIR to A1–A8
FIGURE 9. tPHZ and tPLZ Test Load and Waveforms
DIR to B1–B8
9
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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