74VCX162244MTDX_NL [FAIRCHILD]
Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48;
| 型号： | 74VCX162244MTDX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48 驱动器 |
| 文件： | 总10页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1997
Revised June 2005
74VCX162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistor in Outputs
General Description
The VCX162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
Features
■ 1.2V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
■ 26 series resistors in outputs
■ tPD
The 74VCX162244 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V. The
3.3 ns max for 3.0V to 3.6V VCC
74VCX162244 is also designed with 26 series resistors in
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal
■ Static Drive (IOH/IOL
)
12 mA @ 3.0V VCC
The 74VCX162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model 2000V
Machine model 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
through a pull-up resistor; the minimum
CC
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
Package Description
74VCX162244G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX162244MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500040
www.fairchildsemi.com
Connection Diagrams
Pin Descriptions
Pin Assignment for TSSOP
Pin Names
Description
OEn
I0–I15
O0–O15
NC
Output Enable Input (Active LOW)
Inputs
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
OE2
NC
NC
I1
I0
I2
O4
O3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
I3
I4
O6
O5
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
I11
I13
J
O15
NC
OE4
OE3
NC
I15
Truth Tables
Inputs
Outputs
Pin Assignment for FBGA
OE1
L
I0–I3
L
O0–O3
L
H
Z
L
H
H
X
Inputs
OE2
Outputs
O4–O7
I4–I7
L
L
L
H
X
L
H
Z
H
(Top Thru View)
Inputs
OE3
Outputs
O8–O11
I8–I11
L
L
L
H
X
L
H
Z
H
Inputs
OE4
Outputs
O12–O15
I12–I15
L
L
L
H
X
L
H
Z
H
H
L
HIGH Voltage Level
LOW Voltage Level
X
Z
Immaterial (HIGH or LOW, inputs may not float)
High Impedance
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2
Functional Description
The 74VCX162244 contains sixteen non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 16-bit operation.The 3-STATE out-
puts are controlled by an Output Enable (OEn) input. When
OEn is LOW, the outputs are in the 2-state mode. When
OEn is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
Logic Diagram
3
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Absolute Maximum Ratings(Note 4)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.2V to 3.6V
1.2V to 3.6V
0.3V to 3.6V
Outputs 3-STATE
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Data Retention Only
Input Voltage
Outputs Active (Note 5)
DC Input Diode Current (IIK) VI 0V
Output Voltage (VO)
Output in Active States
Output in 3-State
DC Output Diode Current (IOK
VO 0V
)
0V to VCC
50 mA
50 mA
0.0V to 3.6V
VO VCC
Output Current in IOH/IOL
VCC 3.0V to 3.6V
VCC 2.3V to 2.7V
VCC 1.65V to 2.3V
VCC 1.4V to 1.6V
VCC 1.2V
DC Output Source/Sink Current
(IOH/IOL
12 mA
8 mA
3 mA
2 mA
)
50 mA
DC VCC or GND Current per
Supply Pin (ICC or GND)
100 mA
Storage Temperature Range (TSTG
)
65 C to 150 C
100 A
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V ꢀ V d 3.6V)
CC
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
V
V
V
HIGH Level Input Voltage
2.7 - 3.6
2.3 - 2.7
2.0
1.6
IH
1.65 - 2.3 0.65 x V
V
CC
CC
CC
1.4 - 1.6
1.2
0.65 x V
0.65 x V
LOW Level Input Voltage
HIGH Level Output Voltage
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
1.2
0.8
0.7
IL
0.35 x V
0.35 x V
V
CC
CC
CC
0.5 x V
I
100
A
2.7 - 3.6
2.7
V
V
- 0.2
CC
OH
OH
I
6 mA
8 mA
2.2
OH
I
3.0
2.4
2.2
OH
I
12 mA
3.0
OH
I
100
A
2.7 - 3.6
2.3
- 0.2
CC
OH
I
4 mA
6 mA
8 mA
100
2.0
1.8
1.7
OH
I
2.3
V
OH
I
2.3
OH
I
A
1.65 - 2.3
1.65
V
V
V
- 0.2
CC
OH
I
3 mA
100
1.25
- 0.2
CC
OH
I
A
A
1.4 - 1.6
1.4
OH
I
1 mA
100
1.05
- 0.1
CC
OH
I
1.2
OH
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4
DC Electrical Characteristics (2.7V < VCC £ 3.6V) (Continued)
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
V
LOW Level Output Voltage
I
I
I
I
I
I
I
I
I
I
I
I
100
A
0.2
0.4
0.55
0.8
0.2
0.4
0.6
0.2
0.3
0.2
0.35
0.1
5.0
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
6 mA
8 mA
3.0
12 mA
3.0
100
A
2.7 - 3.6
2.3
6 mA
8 mA
100
V
2.3
A
A
A
1.65 - 2.3
1.65
3 mA
100
1.4 - 1.6
1.4
1 mA
100
1.2
I
I
Input Leakage Current
0
0
V
0
V
V
3.6V
3.6V
1.2 - 3.6
A
A
I
I
3-STATE Output Leakage
OZ
O
1.2 - 3.6
10
V
or V
IL
I
IH
I
I
Power-OFF Leakage Current
Quiescent Supply Current
(V , V )
3.6V
or GND
CC
0
10
20
OFF
CC
I
O
A
V
V
1.2 - 3.6
1.2 - 3.6
2.7 - 3.6
I
V
V
(V , V )
O
3.6V (Note 7)
20
A
A
CC
IH
I
I
Increase in I per Input
V 0.6V
CC
750
CC
CC
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics (Note 8)
V
T
A
40 C to 85 C
Figure
CC
Symbol
Parameter
Propagation Delay
Conditions
Units
(V)
Min
0.8
1.0
1.5
1.0
1.5
0.8
1.0
1.5
1.0
1.5
0.8
1.0
1.5
1.0
1.5
Max
3.3
3.8
7.6
15.2
38
Number
t
,
C
30 pF, R
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
Figures
1, 2
PHL
L
L
t
PLH
ns
ns
ns
ns
C
C
15 pF, R
30 pF, R
2k
L
L
Figures
5, 6
t
t
,
Output Enable Time
Output Disable Time
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
3.8
5.1
9.8
19.6
49
PZL
L
L
Figures
1, 3, 4
PZH
C
C
15 pF, R
30 pF, R
2k
L
L
Figures
5, 7, 8
t
t
,
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
3.6
4.0
7.2
14.4
36
PLZ
L
L
Figures
1, 3, 4
PHZ
C
C
15 pF, R
30 pF, R
2k
L
L
Figures
5, 7, 8
t
t
Output to Output Skew
(Note 9)
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
0.5
0.5
0.75
1.5
1.5
OSHL
OSLH
L
L
C
15 pF, R
2k
L
L
Note 8: For C
50 F, add approximately 300 ps to the AC maximum specification.
P
L
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
5
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Dynamic Switching Characteristics
V
T
25 C
Typical
CC
A
Symbol
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
V
V
V
Quiet Output Dynamic Peak V
C
C
C
30 pF, V
30 pF, V
30 pF, V
V
V
V
, V
, V
, V
0V
0V
0V
0.15
0.25
0.35
0.15
0.25
0.35
1.55
2.05
2.65
OLP
OL
L
L
L
IH
IH
IH
CC
CC
CC
IL
IL
IL
V
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
OLV
OL
V
V
OHV
OH
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
1.8, 2.5V or 3.3V, V 0V or V
CC
Units
Typical
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
6
7
pF
pF
pF
IN
CC
I
C
V
V
0V or V , V
CC
1.8V, 2.5V or 3.3V
OUT
PD
I
I
CC
C
0V or V , f 10 MHz, V
CC
1.8V, 2.5V or 3.3V
20
CC
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6
AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.15V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
t
PZL, tPLZ
6V at VCC 3.3 0.3V;
V
CC x 2 at VCC 2.5 0.2V; 1.8 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
VOL 0.15V
VOH 0.15V
VY
7
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AC Loading and Waveforms (V 1.5V r 0.1V to 1.2V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
VCC x 2 at VCC 1.5V 0.1V
GND
tPZL, tPLZ
PZH, tPHZ
t
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
VOL 0.1V
VOL 0.1V
VY
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8
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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