74VCX16722MTDX_NL
更新时间:2024-09-18 19:12:35
品牌:FAIRCHILD
描述:Bus Driver, ALVC/VCX/A Series, 1-Func, 22-Bit, True Output, CMOS, PDSO64, 6.10 MM, MO-153EF, TSSOP-64
74VCX16722MTDX_NL 概述
Bus Driver, ALVC/VCX/A Series, 1-Func, 22-Bit, True Output, CMOS, PDSO64, 6.10 MM, MO-153EF, TSSOP-64 总线驱动器/收发器
74VCX16722MTDX_NL 规格参数
是否Rohs认证: | 符合 | 生命周期: | Obsolete |
零件包装代码: | TSSOP | 包装说明: | TSSOP, TSSOP64,.32,20 |
针数: | 64 | Reach Compliance Code: | compliant |
风险等级: | 5.68 | 系列: | ALVC/VCX/A |
JESD-30 代码: | R-PDSO-G64 | JESD-609代码: | e3 |
长度: | 17 mm | 负载电容(CL): | 30 pF |
逻辑集成电路类型: | BUS DRIVER | 最大I(ol): | 0.024 A |
湿度敏感等级: | 2 | 位数: | 22 |
功能数量: | 1 | 端口数量: | 2 |
端子数量: | 64 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 输出特性: | 3-STATE |
输出极性: | TRUE | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | TSSOP | 封装等效代码: | TSSOP64,.32,20 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
包装方法: | TAPE AND REEL | 峰值回流温度(摄氏度): | 260 |
电源: | 3.3 V | 传播延迟(tpd): | 9.2 ns |
认证状态: | Not Qualified | 座面最大高度: | 1.2 mm |
子类别: | FF/Latches | 最大供电电压 (Vsup): | 3.6 V |
最小供电电压 (Vsup): | 1.65 V | 标称供电电压 (Vsup): | 1.8 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子面层: | Matte Tin (Sn) |
端子形式: | GULL WING | 端子节距: | 0.5 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
触发器类型: | POSITIVE EDGE | 宽度: | 6.1 mm |
Base Number Matches: | 1 |
74VCX16722MTDX_NL 数据手册
通过下载74VCX16722MTDX_NL数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载February 1999
Revised January 2005
74VCX16722
Low Voltage 22-Bit Register
with 3.6V Tolerant Inputs and Outputs
General Description
Features
■ 1.65V–3.6V VCC supply operation
The VCX16722 low voltage 22-bit register contains twenty-
two non-inverting D-type flip-flops with 3-STATE outputs
and is intended for bus oriented applications. The design
has been optimized for use with JEDEC compliant 200 pin
DIMM modules.
■ 3.6V tolerant inputs and outputs
■ tPD (CLK to On)
3.6ns max for 3.0V to 3.6V VCC
4.6ns max for 2.3V to 2.7V VCC
9.2ns max for 1.65V to 1.95V VCC
The 74VCX16722 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Meets JEDEC registered module specifications
The 74VCX16722 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Static Drive (IOH/IOL
)
±24mA @ 3.0V
±18mA @ 2.3V
±6mA @ 1.65V
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16722MTD
MTD64
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS500192
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input (Active LOW)
Clock Enable Input (Active Low)
Clock Input
CE
CLK
D0- D21
Data Inputs
O0 - O21
3-STATE Outputs
Truth Table
CLK
CE
OE
Dn
On
X
X
H
L
H
L
L
L
L
X
X
L
Z
On
L
X
↑
↑
L
H
X
H
L or H
L
On
H = Logic HIGH
L = Logic LOW
X = Don’t Care, but not floating
Z = High Impedance
On = Previous On before LOW-to-HIGH Clock Transition
↑ = LOW-to-HIGH Clock Transition
Functional Description
Logic Diagram
The VCX16722 contains twenty-two D-type flip-flops with
3-STATE standard outputs. The twenty-two flip-flops will
store the state of their individual D-type inputs that meet
the setup and hold time requirements on the LOW-HIGH
Clock (CLK) transition, when the Clock-Enable (CE) is
LOW. The 3-STATE standard outputs are controlled by the
Output-Enable (OE). When OE is HIGH, the standard out-
puts are in high impedance mode but this does not inter-
fere with entering new data into the flip-flops.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Output Voltage (VO)
Outputs 3-STATE
Power Supply
Operating
1.65V to 3.6V
1.2V to 3.6V
−0.3V to 3.6V
−0.5V to +4.6V
Data Retention Only
Input Voltage
Outputs Active (Note 3)
−0.5V to VCC +
0.5V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
Output Current in IOH/IOL
DC Input Diode Current (IIK) VI < 0V
−50 mA
0V to VCC
0V to 3.6V
DC Output Diode Current (IOK
)
V
V
O < 0V
−50 mA
+50 mA
O > VCC
V
V
V
CC = 3.0V to 3.6V
CC = 2.3V to 2.7V
CC = 1.65V to 2.3V
±24 mA
±18 mA
DC Output Source/Sink Current
(IOH/IOL
)
±50 mA
±6 mA
DC VCC or Ground Current per
Supply Pin (ICC or Ground)
Free Air Operating Temperature (TA)
−40°C to +85°C
±100 mA
Minimum Input Edge Rate (∆t/∆V)
Storage Temperature Range (TSTG
)
−65°C to +150°C
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < V ≤ 3.6V)
CC
VCC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7–3.6
2.7–3.6
2.7–3.6
2.7
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
2.0
V
V
VIL
0.8
VOH
I
I
I
I
I
I
I
I
OH = −100 µA
V
CC − 0.2
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 12 mA
OL = 18 mA
OL = 24 mA
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.7–3.6
2.7
0.2
0.4
3.0
0.4
3.0
0.55
±5.0
II
Input Leakage Current
0V ≤ VI ≤ 3.6V
2.7–3.6
µA
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
0V ≤ VO ≤ 3.6V
VI = VIH or VIL
2.7–3.6
0
±10
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
0V ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
10
20
2.7–3.6
2.7–3.6
V
CC ≤ (VI, VO) ≤ 3.6V (Note 5)
IH = VCC − 0.6V
±20
750
∆ICC
Increase in ICC per Input
V
Note 5: Outputs disabled or 3-STATE only.
3
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DC Electrical Characteristics (2.3V ≤ V ≤ 2.7V)
CC
VCC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.3–2.7
2.3–2.7
2.3–2.7
2.3
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
1.6
V
V
VIL
0.7
VOH
I
I
I
I
I
I
I
OH = −100 µA
V
CC − 0.2
2.0
OH = −6 mA
OH = −12 mA
OH = −18 mA
OL = 100 µA
OL = 12mA
V
2.3
1.8
2.3
1.7
VOL
LOW Level Output Voltage
2.3–2.7
2.3
0.2
0.4
V
OL = 18 mA
2.3
0.6
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
2.3–2.7
±5.0
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
2.3–2.7
0
±10
VI = VIH or VIL
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
10
20
2.3–2.7
V
CC ≤ (VI, VO) ≤ 3.6V (Note 6)
±20
Note 6: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V ≤ V < 2.3V)
CC
VCC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
1.65 - 2.3
1.65 - 2.3
1.65 - 2.3
1.65
0.65 × VCC
V
V
VIL
0.35 × VCC
VOH
I
I
I
I
OH = −100 µA
V
CC − 0.2
V
OH = −6 mA
OL = 100 µA
OL = 6mA
1.25
VOL
LOW Level Output Voltage
1.65 - 2.3
1.65
0.2
0.3
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
1.65 - 2.3
±5.0
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
1.65 - 2.3
0
±10
VI = VIH or VIL
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
10
20
1.65 - 2.3
V
CC ≤ (VI, VO) ≤ 3.6V (Note 7)
±20
Note 7: Outputs disabled or 3-STATE only.
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4
AC Electrical Characteristics (Note 8)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
V
CC = 3.3V ± 0.3V CC = 2.5 ± 0.2V CC = 1.8 ± 0.15V
V
V
Units
Min
Max
Min
200
1.5
0.8
0.8
2.0
0.0
1.5
Max
Min
Max
fMAX
PHL, tPLH
Maximum Clock Frequency
Propagation Delay Clock to Bus
Output Enable Time
Output Disable Time
Setup Time
250
1.3
0.6
0.6
2.0
0.0
1.5
100
2.0
1.5
1.5
3.0
0.5
4.0
MHz
ns
t
3.6
3.5
3.2
4.6
4.5
4.2
9.2
9.0
7.6
tPZL, tPZH
tPLZ, tPHZ
tS
ns
ns
ns
tH
Hold Time
ns
tW
Pulse Width
ns
tOSHL
tOSLH
Output to Output Skew
(Note 9)
0.5
0.5
0.75
ns
Note 8: For CL= 50 pF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
AC Electrical Characteristics Over Load (Note 10)
TA = −0°C to +70°C, RL = 500Ω VCC = 3.3V ± 0.3V
Symbol
Parameter
C
L = 0 pF L = 50 pF
C
Units
Min
1.1
0.7
0.7
2.0
0.0
1.5
Max
2.5
Min
1.9
1.0
1.0
2.0
0.0
1.5
Max
3.9
t
PHL, tPLH
Propagation Delay Clock to Bus
Output Enable Time
Output Disable Time
Setup Time
ns
ns
ns
ns
ns
ns
tPZL, tPZH
2.4
3.8
3.5
tPLZ, tPHZ
2.1
tS
tH
tW
Hold Time
Pulse Width
Note 10: This parameter is guaranteed by characterization but not tested.
Dynamic Switching Characteristics
VCC
T
A = +25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.25
0.6
Quiet Output Dynamic Peak VOL
C
C
C
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
V
V
V
0.8
VOLV
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
−0.25
−0.6
−0.8
1.5
VOHV
1.9
2.2
5
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Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
Typical
3.5
CIN
Input Capacitance
VI = 0V or VCC, VCC = 1.8V, 2.5V, or 3.3V,
VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
pF
pF
pF
CI/O
CPD
Input/Output Capacitance
5.5
Power Dissipation Capacitance
13
I
- V
Characteristics
OUT
OUT
IOH versus VOH
FIGURE 1. Characteristics for Output - Pull Up Driver
IOL versus VOL
FIGURE 2. Characteristics for Output - Pull Down Driver
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6
AC Loading and Waveforms
FIGURE 3. AC Test Circuit
SWITCH
TEST
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V
tPZH, tPHZ
GND
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
tr = tf ≤ 2.0ns, 10% to 90%
tr = tf ≤ 2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
tr = tf ≤ 2.0ns, 10% to 90%
VCC
Symbol
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC/2
1.8 ± 0.15V
VCC/2
Vmi
Vmo
Vx
1.5V
VCC/2
VCC/2
V
V
OL + 0.3V
OH − 0.3V
V
V
OL + 0.15V
OH − 0.15V
V
V
OL + 0.15V
OH − 0.15V
Vy
7
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Physical Dimensions inches (millimeters) unless otherwise noted
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD64
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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