74VCX16841MEAX [FAIRCHILD]

暂无描述;


型号：	74VCX16841MEAX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	暂无描述锁存器
文件：	总9页 (文件大小：146K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

March 1998

Revised October 2004

74VCX16841

Low Voltage 20-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs

General Description

Features

■ 1.4V to 3.6V V_CCsupply operation

The VCX16841 contains twenty non-inverting latches with

3-STATE outputs and is intended for bus oriented applica-

tions. The device is byte controlled. The flip-flops appear

transparent to the data when the Latch enable (LE) is

HIGH. When LE is LOW, the data that meets the setup time

is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

■ 3.6V tolerant inputs and outputs

■ t_PD(D_nto O_n)

3.0 ns max for 3.0V to 3.6V V_CC

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal (Note 1)

■ Static Drive (I_OH/I_OL

)

The 74VCX16841 is designed for low voltage (1.4V to

3.6V) V_CCapplications with I/O compatibility up to 3.6V.

±24 mA @ 3.0V V_CC

The 74VCX16841 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

■ Uses patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 300 mA

■ ESD performance:

Human body model > 2000V

Machine model > 200V

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CCthrough a pull-up resistor; the minimum

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Order Number Package Number

Package Description

74VCX16841MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

Description

OE_n

LE_n

Output Enable Input (Active LOW)

Latch Enable Input

Inputs

D₀–D₁₉

O₀–O₁₉

Outputs

DS500132

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Connection Diagram

Truth Tables

Inputs

OE₁

Outputs

O₀–O₉

LE₁

D₀–D₉

O₀

Inputs

OE₂

Outputs

O₁₀–O₁₉

LE₂

D₁₀–D₁₉

O₀

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial (HIGH or LOW, inputs may not float)

Z = High Impedance

O₀= Previous O₀before HIGH-to-LOW of Latch Enable

Functional Description

The 74VCX16841 contains twenty D-type latches with

3-STATE outputs. The device is byte controlled with each

byte functioning identically, but independent of the other.

Control pins can be shorted together to obtain full 20-bit

operation. The following description applies to each byte.

When the Latch Enable (LE_n) input is HIGH, data on the D_n

D-type input changes. When LE_nis LOW, the latches store

information that was present on the D-type inputs a setup

time preceding the HIGH-to-LOW transition on LE_n. The

3-STATE outputs are controlled by the Output Enable

(OE_n) input. When OE_nis LOW the standard outputs are in

the 2-state mode. When OE_nis HIGH, the standard outputs

enters the latches. In this condition the latches are trans-

parent, i.e., a latch output will change states each time its

are in the high impedance mode but this does not interfere

with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 2)

Recommended Operating

Conditions ^{(Note 4)}

Supply Voltage (V_CC

)

−0.5V to +4.6V

DC Input Voltage (V_I)

Power Supply

Output Voltage (V_O)

Operating

1.4V to 3.6V

Outputs 3-STATE

−0.5V to +4.6V

−0.5V to V_CC+ 0.5V

−50 mA

Input Voltage

−0.3V to +3.6V

Outputs Active (Note 3)

DC Input Diode Current (I_IK) V_I< 0V

Output Voltage (V_O)

Output in Active States

Output in 3-STATE

Output Current in I_OH/I_OL

0V to V_CC

DC Output Diode Current (I_OK

)

0.0V to 3.6V

V_O< 0V

−50 mA

+50 mA

V_O> V_CC

_CC= 3.0V to 3.6V

_CC= 2.3V to 2.7V

_CC= 1.65V to 2.3V

_CC= 1.4V to 1.6V

±24 mA

±18 mA

DC Output Source/Sink Current

(I_OH/I_OL

)

±50 mA

±6 mA

DC V_CCor GND Current per

Supply Pin (I_CCor GND)

±2 mA

±100 mA

Free Air Operating Temperature (T_A)

−40°C to +85°C

Storage Temperature Range (T_STG

)

−65°C to +150°C

Minimum Input Edge Rate (∆t/∆V)

_IN= 0.8V to 2.0V, V_CC= 3.0V

10 ns/V

Note 2: The Absolute Maximum Ratings are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The “Recommended Operating Conditions” table will define the condi-

tions for actual device operation.

Note 3: I_OAbsolute Maximum Rating must be observed.

Note 4: Floating or unused inputs must be held HIGH or LOW.

DC Electrical Characteristics

V_CC

Symbol

V_IH

Parameter

Conditions

Min

Max

Units

(V)

HIGH Level Input Voltage

2.7 - 3.6

2.3 - 2.7

2.0

1.6

1.65 - 2.3 0.65 x V_CC

1.4 - 1.6

2.7 - 3.6

2.3 - 2.7

1.65 - 2.3

1.4 - 1.6

2.7 - 3.6

2.7

0.65 x V_CC

V_IL

LOW Level Input Voltage

HIGH Level Output Voltage

0.8

0.7

0.35 x V_CC

V_OH

_OH= −100 µA

_OH= −12 mA

_OH= −18 mA

_OH= −24 mA

_OH= −100 µA

_OH= −6 mA

_OH= −12 mA

_OH= −18 mA

_OH= −100 µA

_OH= −6 mA

_OH= −100 µA

_OH= −2 mA

V_CC- 0.2

2.2

3.0

2.4

3.0

2.2

2.3 - 2.7

2.3

V_CC- 0.2

2.0

2.3

1.8

2.3

1.7

1.65 - 2.3

1.65

V_CC- 0.2

1.25

1.4 - 1.6

1.4

V_CC- 0.2

1.05

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DC Electrical Characteristics (Continued)

V_CC

Symbol

V_OL

Parameter

Conditions

Min

Max

Units

(V)

2.7 - 3.6

2.7

LOW Level Output Voltage

_OL= 100 µA

_OL= 12 mA

_OL= 18 mA

_OL= 24 mA

_OL= 100 µA

_OL= 12 mA

_OL= 18 mA

_OL= 100 µA

_OL= 6 mA

0.2

0.4

3.0

0.4

3.0

0.55

0.2

2.3 - 2.7

2.3

0.4

2.3

0.6

1.65 - 2.3

1.65

0.2

0.3

_OL= 100 µA

_OL= 2 mA

1.4 - 1.6

1.4

0.2

0.35

±5.0

I_I

Input Leakage Current

0 ≤ V_I≤ 3.6V

0 ≤ V_O≤ 3.6V

V_I= V_IHor V_IL

1.4 - 3.6

µA

I_OZ

3-STATE Output Leakage

1.4 - 3.6

±10.0

I_OFF

I_CC

Power-OFF Leakage Current

Quiescent Supply Current

0 ≤ (V_I, V_O) ≤ 3.6V

V_I= V_CCor GND

10.0

20.0

µA

1.4 - 3.6

2.7 - 3.6

_CC≤ (V_I, V_O) ≤ 3.6V (Note 5)

_IH= V_CC−0.6V

±20.0

750

∆I_CC

Increase in I_CCper Input

Note 5: Outputs disabled or 3-STATE only.

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AC Electrical Characteristics (Note 6)

V_CC

T_A= −40°C to +85°C

Figure

Symbol

Parameter

Conditions

Units

(V)

Min

0.8

1.0

1.5

1.0

Max

3.0

Number

t_PHL

Propagation Delay

_L= 30 pF, R_L= 500Ω

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

Figures

1, 2

t_PLH

D_nto O_n

3.4

6.8

_L= 15 pF, R_L= 2kΩ

_L= 30 pF, R_L= 500Ω

13.6

Figures

7, 8

t_PHL

t_PLH

Propagation Delay

LE to O_n

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

0.8

1.0

1.5

1.0

3.5

4.4

Figures

1, 2

8.8

_L= 15 pF, R_L= 500Ω

_L= 30 pF, R_L= 500Ω

17.6

Figures

7, 8

t_PZL

t_PZH

Output Enable Time

Output Disable Time

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

0.8

1.0

1.5

1.0

3.8

4.9

Figures

1, 3, 4

9.8

_L= 15 pF, R_L= 2kΩ

_L= 30 pF, R_L= 500Ω

19.6

Figures

7, 9, 10

t_PLZ

t_PHZ

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

0.8

1.0

1.5

1.0

3.7

4.2

Figures

1, 3, 4

7.6

_L= 15 pF, R_L= 2kΩ

_L= 30 pF, R_L= 500Ω

15.2

Figures

7, 9, 10

t_S

Setup Time

Hold Time

Pulse Width

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

1.5

2.5

3.0

1.0

2.0

1.5

4.0

Figure 6

Figure 5

_L= 15 pF, R_L= 500Ω

_L= 30 pF, R_L= 500Ω

t_H

_L= 15 pF, R_L= 500Ω

_L= 30 pF, R_L= 500Ω

t_W

_L= 15 pF, R_L= 500Ω

_L= 30 pF, R_L= 500Ω

t_OSHL

t_OSLH

Output to Output Skew

(Note 7)

0.5

0.75

1.5

_L= 15 pF, R_L= 2kΩ

Note 6: For C_L= 50 _PF, add approximately 300 ps to the AC maximum specification.

Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH).

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Dynamic Switching Characteristics

V_CC

_A= +25°C

Symbol

V_OLP

Parameter

Conditions

Units

(V)

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

Typical

0.25

0.6

Quiet Output Dynamic Peak V_OL

_L= 30 pF, V_IH= V_CC, V_IL= 0V

0.8

V_OLV

Quiet Output Dynamic Valley V_OL

Quiet Output Dynamic Valley V_OH

_L= 30 pF, V_IH= V_CC, V_IL= 0V

−0.25

−0.6

−0.8

1.5

V_OHV

1.9

2.2

Capacitance

_A= +25°C

Symbol

Parameter

Conditions

_CC= 1.8V, 2.5V or 3.3V, V_I= 0V or V_CC

Units

Typical

6.0

C_IN

Input Capacitance

Output Capacitance

Power Dissipation Capacitance

C_OUT

C_PD

V_I= 0V or V_CC, V_CC= 1.8V, 2.5V or 3.3V

V_I= 0V or V_CC, f = 10 MHz,

7.0

20.0

_CC= 1.8V, 2.5V or 3.3V

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AC Loading and Waveforms (V 3.3V ± 0.3V to 1.8V ± 0.15V)

TEST

t_PLH, t_PHL

t_PZL, t_PLZ

SWITCH

Open

6V at V_CC= 3.3V ± 0.3V;

V_CCx 2 at V_CC= 2.5V ± 0.2V; 1.8V ± 0.15V

t_PZH, t_PHZ

GND

FIGURE 1. AC Test Circuit

FIGURE 3. 3-STATE Output High Enable and

Disable Times for Low Voltage Logic

FIGURE 2. Waveform for Inverting and

Non-Inverting Functions

FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

FIGURE 5. Propagation Delay, Pulse Width and

FIGURE 6. Setup Time, Hold Time and

Recovery Time for Low Voltage Logic

_recWaveforms

V_CC

Symbol

3.3V ± 0.3V

1.5V

2.5V ± 0.2V

V_CC/2

1.8V ± 0.15V

V_CC/2

V_mi

V_mo

V_X

1.5V

V_CC/2

_OL+ 0.3V

_OL+ 0.15V

V_Y

_OH− 0.3V

_OH− 0.15V

V_OH− 0.15V

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AC Loading and Waveforms (V 1.5V ± 0.1V)

TEST

t_PLH, t_PHL

t_PZL, t_PLZ

t_PZH, t_PHZ

SWITCH

Open

V_CCx 2 at V_CC= 1.5 ± 0.1V

GND

FIGURE 7. AC Test Circuit

FIGURE 8. Waveform for Inverting and Non-Inverting Functions

FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

V_CC

Symbol

1.5V ± 0.1V

V_mi

V_mo

V_X

V_CC/2

_OL+ 0.1V

V_Y

V_OH− 0.1V

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Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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74VCX16841MEAX [FAIRCHILD]

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