74VCX32244G [FAIRCHILD]

Low Voltage 32-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs; 低电压32位缓冲器/线路与3.6V容限输入和输出驱动器


型号：	74VCX32244G
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Low Voltage 32-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs 低电压32位缓冲器/线路与3.6V容限输入和输出驱动器总线驱动器总线收发器逻辑集成电路
文件：	总9页 (文件大小：109K)
中文：	中文翻译
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September 2000

Revised November 2002

74VCX32244

Low Voltage 32-Bit Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX32244 contains thirty-two non-inverting buffers

with 3-STATE outputs to be employed as a memory and

Features

■ 1.2V to 3.6V V_CCsupply operation

■ 3.6V tolerant inputs and outputs

■ t_PD

2.5 ns max for 3.0V to 3.6V V_CC

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for 8-bit, 16-bit or full 32-bit operation.

The 74VCX32244 is designed for low voltage (1.2V to

3.6V) V_CCapplications with I/O capability up to 3.6V.

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal (Note 1)

The 74VCX32244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

■ Static Drive (I_OH/I_OL

)

±24 mA @ 3.0V V_CC

■ Uses patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 300 mA

■ ESD performance:

Human body model > 2000V

Machine model > 200V

■ Packages in plastic Fine-Pitch Ball Grid Array (FBGA)

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CCthrough a pull-up resistor; the minimum

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Order Number Package Number

Package Description

74VCX32244G

(Note 2)(Note 3)

BGA96A

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

DS500416

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Connection Diagram

Truth Tables

Inputs

OE₁

Outputs

O₀-O₃

I₀-I₃

Inputs

OE₂

Outputs

O₄-O₇

I₄-I₇

Inputs

OE₃

Outputs

O₈–O₁₁

I₈-I₁₁

Inputs

OE₄

Outputs

O₁₂-O₁₅

(Top Thru View)

I₁₂-I₁₅

Pin Descriptions

Pin Names

Description

OE_n

Output Enable Input (Active LOW)

Inputs

OE₅

Outputs

O₁₆-O₁₉

I₀–I₃₁

O₀–O₃₁

Inputs

I₁₆-I₁₉

Outputs

FBGA Pin Assignments

Inputs

OE₆

Outputs

O₂₀-O₂₃

O₁

O₃

O₀

O₂

OE₁

OE₂

I₀

I₂

I₁

I₃

I₂₀-I₂₃

GND GND

V_CCV_CC

O₅

O₄

I₄

I₅

O₇

O₆

GND GND

I₆

I₇

O₉

O₈

I₈

I₉

O₁₁

O₁₃

O₁₀

O₁₂

V_CC

I₁₀

I₁₂

I₁₁

I₁₃

Inputs

OE₇

Outputs

O₂₄-O₂₇

GND GND

I₂₄-I₂₇

O₁₄

O₁₅

OE₄

OE₅

OE₃

OE₆

I₁₅

I₁₄

O₁₇

O₁₉

O₂₁

O₂₃

O₂₅

O₂₇

O₂₉

O₁₆

0₁₈

I₁₆

I₁₈

I₂₀

I₂₂

I₂₄

I₂₆

I₂₈

I₁₇

I₁₉

I₂₁

I₂₃

I₂₅

I₂₇

I₂₉

GND GND

V_CCV_CC

O₂₀

O₂₂

O₂₄

O₂₆

O₂₈

Inputs

OE₈

Outputs

O₂₈-O₃₁

GND GND

I₂₈-I₃₁

V_CC

GND GND

OE₈OE₇

V_CC

O₃₀

O₃₁

I₃₁

I₃₀

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial (HIGH or LOW, inputs may not float)

Z = High Impedance

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Functional Description

The 74VCX32244 contains thirty-two non-inverting buffers

with 3-STATE outputs. The device is nibble (4 bits) con-

trolled with each nibble functioning identically, but indepen-

dent of each other. The control pins may be shorted

together to obtain full 32-bit operation.The 3-STATE out-

puts are controlled by an Output Enable (OE_n) input. When

OE_nis LOW, the outputs are in the 2-state mode. When

OE_nis HIGH, the standard outputs are in the high imped-

ance mode but this does not interfere with entering new

data into the inputs.

Logic Diagrams

Byte 1

Byte 2

Byte 3

Byte 4

Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 4)

Recommended Operating

Conditions ^{(Note 6)}

Supply Voltage (V_CC

)

−0.5V to +4.6V

DC Input Voltage (V_I)

Power Supply

Output Voltage (V_O)

Operating

1.2V to 3.6V

Outputs 3-STATED

−0.5V to +4.6V

−0.5V to V_CC+0.5V

−50 mA

Input Voltage

−0.3V to +3.6V

Outputs Active (Note 5)

DC Input Diode Current (I_IK) V_I< 0V

Output Voltage (V_O)

Output in Active States

Output in 3-STATE

Output Current in I_OH/I_OL

0V to V_CC

DC Output Diode Current (I_OK

)

0.0V to 3.6V

_O< 0V

−50 mA

+50 mA

_O> V_CC

_CC= 3.0V to 3.6V

_CC= 2.3V to 2.7V

_CC= 1.65V to 2.3V

_CC= 1.2V

±24 mA

±18 mA

DC Output Source/Sink Current

(I_OH/I_OL

)

±50 mA

±6 mA

DC V_CCor GND Current per

Supply Pin (I_CCor GND)

±100 µA

±100 mA

Free Air Operating Temperature (T_A)

−40°C to +85°C

Storage Temperature Range (T_STG

)

−65°C to +150°C

Minimum Input Edge Rate (∆t/∆V)

_IN= 0.8V to 2.0V, V_CC= 3.0V

10 ns/V

Note 4: The Absolute Maximum Ratings are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The “Recommended Operating Conditions” table will define the condi-

tions for actual device operation.

Note 5: I_OAbsolute Maximum Rating must be observed.

Note 6: Floating or unused inputs must be held HIGH or LOW.

DC Electrical Characteristics (2.7V < V_CC≤ 3.6V)

V_CC

Symbol

V_IH

Parameter

Conditions

Min

Max

Units

(V)

HIGH Level Input Voltage

2.7 - 3.6

2.3 - 2.7

2.0

1.6

1.65 - 2.3 0.65 x V_CC

1.4 - 1.6

1.2

0.65 x V_CC

V_IL

LOW Level Input Voltage

HIGH Level Output Voltage

2.7 - 3.6

2.3 - 2.7

1.65 - 2.3

1.4 - 1.6

1.2

0.8

0.7

0.35 x V_CC

0.05 x V_CC

V_OH

_OH= −100 µA

_OH= −12 mA

_OH= −18 mA

_OH= −24 mA

_OH= −100 µA

_OH= −6 mA

_OH= −12 mA

_OH= −18 mA

_OH= −100 µA

_OH= −6 mA

_OH= −100 µA

_OH= −2 mA

_OH= −100 µA

2.7 - 3.6

2.7

V_CC- 0.2

2.2

3.0

2.4

3.0

2.2

2.3 - 2.7

2.3

V_CC- 0.2

2.0

2.3

1.8

2.3

1.7

1.65 - 2.3

1.65

V_CC- 0.2

1.25

1.4 - 1.6

1.4

V_CC- 0.2

1.05

1.2

V_CC- 0.2

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DC Electrical Characteristics (Continued)

V_CC

Symbol

V_OL

Parameter

Conditions

Min

Max

Units

(V)

2.7 - 3.6

2.7

LOW Level Output Voltage

_OL= 100 µA

_OL= 12 mA

_OL= 18 mA

_OL= 24 mA

_OL= 100 µA

_OL= 12 mA

_OL= 18 mA

_OL= 100 µA

_OL= 6 mA

0.2

0.4

3.0

0.4

3.0

0.55

0.2

2.3 - 2.7

2.3

0.4

2.3

0.6

1.65 - 2.3

1.65

0.2

0.3

_OL= 100 µA

_OL= 2 mA

1.4 - 1.6

1.4

0.2

0.35

0.05

±5.0

_OL= 100 µA

1.2

I_I

Input Leakage Current

0 ≤ V_I≤ 3.6V

0 ≤ V_O≤ 3.6V

V_I= V_IHor V_IL

1.2 - 3.6

µA

I_OZ

3-STATE Output Leakage

1.2 - 3.6

±10

I_OFF

I_CC

Power-OFF Leakage Current

Quiescent Supply Current

0 ≤ (V_I, V_O) ≤ 3.6V

V_I= V_CCor GND

1.2 - 3.6

2.7 - 3.6

_CC≤ (V_I, V_O) ≤ 3.6V (Note 7)

_IH= V_CC−0.6V

±40

750

∆I_CC

Increase in I_CCper Input

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics (Note 8)

V_CC

T_A= −40°C to +85°C

Figure

Symbol

Parameter

Propagation Delay

Conditions

Units

(V)

Min

0.8

1.0

1.5

1.0

1.5

0.8

1.0

1.5

1.0

1.5

0.8

1.0

1.5

1.0

1.5

Max

2.5

3.0

6.0

12.0

Number

t_PHL

_L= 30 pF, R_L= 500Ω

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

1.2

Figures

1, 2

t_PLH

_L= 15 pF, R_L= 2kΩ

_L= 30 pF, R_L= 500Ω

Figures

5, 6

t_PZL

Output Enable Time

Output Disable Time

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

1.2

3.5

4.1

8.2

16.4

Figures

1, 3, 4

t_PZH

_L= 15 pF, R_L= 2kΩ

_L= 30 pF, R_L= 500Ω

Figures

5, 6, 7

t_PLZ

3.3 ± 0.3

2.5 ± 0.2

1.8 ± 0.15

1.5 ± 0.1

1.2

3.5

3.8

6.8

13.6

Figures

1, 3, 4

t_PHZ

_L= 15 pF, R_L= 2kΩ

Figures

5, 7, 8

Note 8: For C_L= 50_PF, add approximately 300 ps to the AC maximum specification.

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Dynamic Switching Characteristics

V_CC

_A= +25°C

Symbol

V_OLP

Parameter

Conditions

Units

(V)

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

Typical

0.25

0.6

Quiet Output Dynamic Peak V_OL

_L= 30 pF, V_IH= V_CC, V_IL= 0V

0.8

V_OLV

Quiet Output Dynamic Valley V_OL

Quiet Output Dynamic Valley V_OH

_L= 30 pF, V_IH= V_CC, V_IL= 0V

−0.25

−0.6

−0.8

1.5

V_OHV

1.9

2.2

Capacitance

_A= +25°C

Symbol

Parameter

Conditions

_CC= 1.8, 2.5V or 3.3V, V_I= 0V or V_CC

Units

Typical

C_IN

Input Capacitance

Output Capacitance

Power Dissipation Capacitance

C_OUT

C_PD

V_I= 0V or V_CC, V_CC= 1.8V, 2.5V or 3.3V

V_I= 0V or V_CC, f = 10 MHz, V_CC= 1.8V, 2.5V or 3.3V

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AC Loading and Waveforms (V 3.3V ± 0.3V to 1.8V ± 0.15V)

TEST

SWITCH

_PLH, t_PHL

_PZL, t_PLZ

Open

6V at V_CC= 3.3 ± 0.3V;

V_CCx 2 at V_CC= 2.5 ± 0.2V; 1.8V ± 0.15V

t_PZH, t_PHZ

GND

FIGURE 1. AC Test Circuit

FIGURE 2. Waveform for Inverting and Non-Inverting Functions

FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

V_CC

Symbol

3.3V ± 0.3V

1.5V

2.5V ± 0.2V

V_CC/2

1.8V ± 0.15V

V_CC/2

V_mi

V_mo

V_X

1.5V

V_CC/2

_OL+0.3V

_OL+0.15V

V_Y

_OH−0.3V

_OH−0.15V

V_OH−0.15V

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AC Loading and Waveforms (V 1.5 ± 0.1V to 1.2V)

TEST

SWITCH

Open

_PLH, t_PHL

_PZL, t_PLZ

V_CCx 2 at V_CC= 1.5 ± 0.1V

t_PZH, t_PHZ

GND

FIGURE 5. AC Test Circuit

FIGURE 6. Waveform for Inverting and Non-Inverting Functions

FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

V_CC

Symbol

1.5V ± 0.1V

V_mi

V_mo

V_X

V_CC/2

V_OL+0.1V

V_Y

V_OH−0.1V

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Physical Dimensions inches (millimeters) unless otherwise noted

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA96A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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74VCX32244G [FAIRCHILD]

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