74VCXF162835MTX [FAIRCHILD]

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26з Series Resistors in Outputs; 低电压18位通用总线驱动器，具有3.6V输出的宽容和26з系列电阻的输出


型号：	74VCXF162835MTX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26з Series Resistors in Outputs 低电压18位通用总线驱动器，具有3.6V输出的宽容和26з系列电阻的输出总线驱动器总线收发器逻辑集成电路光电二极管
文件：	总8页 (文件大小：78K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

October 1999

Revised November 2000

74VCXF162835

Low Voltage 18-Bit Universal Bus Driver with 3.6V

Tolerant Outputs and 26Ω Series Resistors in Outputs

General Description

The VCXF162835 low voltage 18-bit universal bus driver

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched and clocked modes.

Features

■ Compatible with PC133 DIMM module specifications

■ 1.65V–3.6V V_CCspecifications provided

■ 3.6V tolerant outputs

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

gled. Data transfers from the Inputs (I_n) to Outputs (O_n) on

■ 26Ω series resistors in outputs

■ t_PD(CLK to O_n)

3.2 ns max for 3.0V to 3.6V V_CC

4.1 ns max for 2.3V to 2.7V V_CC

7.4 ns max for 1.65V to 1.95V V_CC

a Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

■ Power-down high impedance outputs

■ Static Drive (I_OH/I_OL

)

The VCXF162835 is designed with 26Ω series resistors in

the outputs. This design reduces noise in applications such

as memory address drivers, clock drivers, and bus trans-

ceivers/transmitters.

±12 mA @ 3.0V V_CC

±8 mA @ 2.3V V_CC

±3 mA @ 1.65V V_CC

The 74VCXF162835 is designed for low voltage (1.65V to

3.6V) V_CCapplications with I/O capability up to 3.6V.

■ Latchup performance exceeds 300 mA

■ ESD performance:

The 74VCXF162835 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Human body model > 2000V

Machine model >200V

Ordering Code:

Package

Order Number

Package Description

Number

74VCXF162835MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TUBES]

74VCXF162835MTX MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

(Note 1)

[TAPE and REEL]

Note 1: Use this Order Number to receive devices in Tape and Reel.

DS500259

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Connection Diagram

Pin Descriptions

Pin Names

Description

Output Enable Input (Active LOW)

Latch Enable Input

Clock Input

CLK

I₁- I₁₈

O₁- O₁₈

Data Inputs

3-STATE Outputs

Truth Table

Inputs

CLK

Outputs

O_n

I_n

↑

O₀(Note 2)

O₀(Note 3)

H = Logic HIGH

L = Logic LOW

X = Don’t Care, but not floating

Z = High Impedance

↑ = LOW-to-HIGH Clock Transition

Note 2: Output level before the indicated steady-state input conditions

were established provided that CLK was HIGH before LE went LOW.

Note 3: Output level before the indicated steady-state input conditions

were established.

Logic Diagram

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Absolute Maximum Ratings(Note 4)

Recommended Operating

Conditions ^{(Note 7)}

Supply Voltage (V_CC

)

−0.5V to +4.6V

DC Input Voltage (V_I)

Output Voltage (V_O)

Outputs 3-STATE

−0.5V to V_CC+ 0.5V

Power Supply

Operating

1.65V to 3.6V

1.2V to 3.6V

−0.3V to V_CC

−0.5V to +4.6V

Data Retention Only

Input Voltage

Outputs Active (Note 5)

DC Input Diode Current (I_IK

V_I< −0.5V

−0.5V to V_CC+ 0.5V

)

Output Voltage (V_O)

Output in Active States

Output in 3-STATE

Output Current in I_OH/I_OL

−50 mA

+50 mA

0V to V_CC

0V to 3.6V

V_I> V_CC+ 0.5V (Note 6)

DC Output Diode Current (I_OK

)

_O< 0V

−50 mA

+50 mA

_CC= 3.0V to 3.6V

_CC= 2.3V to 2.7V

_CC= 1.65V to 2.3V

±12 mA

±8 mA

_O> V_CC

DC Output Source/Sink Current

(I_OH/I_OL

±3 mA

)

±50 mA

Free Air Operating Temperature (T_A)

−40°C to +85°C

DC V_CCor Ground Current per

Supply Pin (I_CCor Ground)

Minimum Input Edge Rate (∆t/∆V)

±100 mA

_IN= 0.8V to 2.0V, V_CC= 3.0V

10 ns/V

Note 4: The “Absolute Maximum Ratings” are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The Recommended Operating Conditions tables will define the condi-

tions for actual device operation.

Storage Temperature Range (T_STG

)

−65°C to +150°C

Note 5: I_OAbsolute Maximum Rating must be observed.

Note 6: Inputs do not have over-voltage tolerance.

Note 7: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.

DC Electrical Characteristics (2.7V < V ≤ 3.6V)

V_CC

Symbol

Parameter

Conditions

Min

Max

Units

(V)

2.7–3.6

2.7

V_IH

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Voltage

2.0

V_IL

0.8

V_OH

_OH= −100 µA

_OH= −6 mA

_OH= −8 mA

_OH= −12 mA

_OL= 100 µA

_OL= 6mA

V_CC− 0.2

2.2

3.0

2.4

3.0

2.2

V_OL

LOW Level Output Voltage

2.7–3.6

2.7

0.2

0.4

_OL= 8 mA

3.0

0.55

0.8

_OL= 12mA

3.0

I_I

Input Leakage Current

V_I= V_CCor GND

0V ≤ V_O≤ 3.6V

V_I= V_IHor V_IL

2.7–3.6

±5.0

µA

I_OZ

3-STATE Output Leakage

2.7–3.6

±10

I_OFF

I_CC

Power Off Leakage Current

Quiescent Supply Current

0V ≤ (V_O) ≤ 3.6V

V_I= V_CCor GND

2.7–3.6

_CC≤ (V_O) ≤ 3.6V (Note 8)

_IH= V_CC− 0.6V

±20

750

∆I_CC

Increase in I_CCper Input

Note 8: Outputs disabled or 3-STATE only.

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DC Electrical Characteristics (2.3V ≤ V ≤ 2.7V)

V_CC

Symbol

Parameter

Conditions

Min

Max

Units

(V)

2.3–2.7

2.3

V_IH

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Voltage

1.6

V_IL

0.7

V_OH

_OH= −100 µA

_OH= −3 mA

_OH= −6 mA

_OH= −8 mA

_OL= 100 µA

_OL= 6 mA

_OL= 8 mA

_CC− 0.2

2.0

2.3

1.8

2.3

1.7

V_OL

LOW Level Output Voltage

2.3–2.7

2.3

0.2

0.4

2.3

0.6

I_I

Input Leakage Current

V_I= V_CCor GND

0V ≤ V_O≤ 3.6V

V_I= V_IHor V_IL

2.3–2.7

±5.0

µA

I_OZ

3-STATE Output Leakage

2.3–2.7

±10

I_OFF

I_CC

Power Off Leakage Current

Quiescent Supply Current

0V ≤ (V_O) ≤ 3.6V

V_I= V_CCor GND

2.3–2.7

V_CC≤ (V_O) ≤ 3.6V (Note 9)

±20

Note 9: Outputs disabled or 3-STATE only.

DC Electrical Characteristics (1.65V ≤ V < 2.3V)

V_CC

(V)

Symbol

Parameter

Conditions

Min

Max

Units

V_IH

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Voltage

1.65 - 2.3 0.65 × V_CC

V_IL

1.65 - 2.3

0.35 × V_CC

V_OH

_OH= −100 µA

_OH= −3 mA

_OL= 100 µA

_OL= 3 mA

1.65 - 2.3

1.65

_CC− 0.2

1.25

V_OL

LOW Level Output Voltage

1.65 - 2.3

1.65

0.2

0.3

I_I

Input Leakage Current

V_I= V_CCor GND

0V ≤ V_O≤ 3.6V

V_I= V_IHor V_IL

1.65 - 2.3

±5.0

µA

I_OZ

3-STATE Output Leakage

1.65 - 2.3

±10

I_OFF

I_CC

Power Off Leakage Current

Quiescent Supply Current

0V ≤ (V_O) ≤ 3.6V

V_I= V_CCor GND

1.65 - 2.3

V_CC≤ (V_O) ≤ 3.6V (Note 10)

±20

Note 10: Outputs disabled or 3-STATE only.

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AC Electrical Characteristics (Note 11)

T_A= −40°C to +85°C, C_L= 30 pF, R_L= 500Ω

Symbol

Parameter

_CC= 3.3V ± 0.3V _CC= 2.5 ± 0.2V _CC= 1.8 ± 0.15V

Units

Min

Max

Min

Max

Min

Max

f_MAX

_PHL, t_PLH

Maximum Clock Frequency

Propagation Delay

Bus to Bus

250

200

100

MHz

0.6

3.1

3.2

3.7

0.8

1.5

0.8

4.0

4.1

4.7

1.5

7.2

7.4

8.5

t_PHL, t_PLH

Propagation Delay

Clock to Bus

1.0

0.6

2.0

1.5

_PHL, t_PLH

Propagation Delay

LE to Bus

_PZL, t_PZH

Output Enable Time

Output Disable Time

Setup Time

0.6

1.5

0.7

1.5

4.3

4.2

0.8

1.5

0.7

1.5

5.9

4.7

1.5

2.5

1.0

4.0

9.8

7.9

t_PLZ, t_PHZ

t_S

t_H

Hold Time

t_W

Pulse Width

t_OSHL

t_OSLH

Output to Output Skew

(Note 12)

0.5

0.75

Note 11: For C_L= 50pF, add approximately 300ps to the AC maximum specification.

Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH).

AC Electrical Characteristics Over Load (Note 13)

_A= −0°C to +85°C, R_L= 500Ω V_CC= 3.3V ± 03V

Symbol

Parameter

C_L= 50 pF

Units

Min

1.0

1.4

1.0

0.6

Max

3.4

3.5

4.0

4.6

4.5

t_PHL, t_PLH

Propagation Delay Bus to Bus

Propagation Delay Clock to Bus

Propagation Delay LE to Bus

Output Enable Time

Output Disable Time

Setup Time

_PHL, t_PLH

t_PHL, t_PLH

t_PZL, t_PZH

_PLZ, t_PHZ

t_S

t_H

Hold Time

Note 13: Characterized only.

Dynamic Switching Characteristics

V_CC

T_A=+25°C

Symbol

V_OLP

Parameter

Conditions

Units

(V)

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

Typical

0.25

Quiet Output Dynamic Peak V_OL

_L= 30 pF, V_IH= V_CC, V_IL= 0V

0.40

0.55

V_OLV

Quiet Output Dynamic Valley V_OL

Quiet Output Dynamic Valley V_OH

−0.25

−0.40

−0.55

1.35

V_OHV

1.80

2.30

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Capacitance

_A= +25°C

Symbol

Parameter

Conditions

Units

Typical

3.5

C_IN

Input Capacitance

V_I= 0V or V_CC, V_CC= 1.8V, 2.5V, or 3.3V,

V_I= 0V, or V_CC, V_CC= 1.8V, 2.5V or 3.3V

V_I= 0V or V_CC, f = 10 MHz, V_CC= 1.8V, 2.5V or 3.3V

C_I/O

C_PD

Input/Output Capacitance

5.5

Power Dissipation Capacitance

- V

Characteristics

OUT

I_OHversus V_OH

FIGURE 1. Characteristics for Output - Pull Up Drive

I_OLversus V_OL

FIGURE 2. Characteristics for Output - Pull Down Driver

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AC Loading and Waveforms

FIGURE 3. AC Test Circuit

SWITCH

TEST

t_PLH, t_PHL

Open

t_PZL, t_PLZ

6V at V_CC= 3.3 ± 0.3V;

V_CCx 2 at V_CC= 2.5 ± 0.2V; 1.8V to ± 0.15V

t_PZH, t_PHZ

GND

FIGURE 4. Waveform for Inverting and

Non-inverting Functions

FIGURE 5. 3-STATE Output High Enable and

Disable Times for Low Voltage Logic

t_r= t_f≤ 2.0ns, 10% to 90%

FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

t_r= t_f≤ 2.0ns, 10% to 90%

V_CC

Symbol

3.3V ± 0.3V

1.5V

2.5V ± 0.2V

V_CC/2

1.8 ± 0.15V

V_CC/2

V_mi

V_mo

V_x

1.5V

V_CC/2

_OL+ 0.3V

_OH− 0.3V

_OL+ 0.15V

_OH− 0.15V

_OL+ 0.15V

_OH− 0.15V

V_y

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Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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74VCXF162835MTX [FAIRCHILD]

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