74VHC541 [FAIRCHILD]
Octal Buffer/Line Driver with 3-STATE Outputs; 八路缓冲器/ 3态输出线路驱动器
| 型号： | 74VHC541 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
Revised May 2005
74VHC541
Octal Buffer/Line Driver with 3-STATE Outputs
An input protection circuit insures that 0V to 7V can be
General Description
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
The VHC541 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
Features
■ High Speed: tPD 3.5 ns (typ) at VCC 5V
■ Low power dissipation: ICC
4 A (max) at TA 25 C
This device is similar in function to the VHC244 while pro-
viding flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
■ High noise immunity: VNIH VNIL 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: VOLP 0.9V (typ)
■ Pin and function compatible with 74HC541
Ordering Code:
Order Number Package Number
Package Description
74VHC541M
74VHC541SJ
74VHC541MTC
74VHC541N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Symbol
IEEE/IEC
Truth Table
Pin Descriptions
Inputs
OE2
Outputs
Pin Names
Descriptions
OE1
I
OE1, OE2
3-STATE Output Enable Inputs
Inputs
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
I0 - I7
O0 - O7
3-STATE Outputs
H
L
HIGH Voltage Level
LOW Voltage Level
X
Z
Immaterial
High Impedance
© 2005 Fairchild Semiconductor Corporation
DS011639
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
)
2.0V to 5.5V
0V to 5.5V
0V to VCC
)
)
)
)
)
20 mA
)
40 C to 85 C
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 3.3V 0.3V
)
75 mA
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
VCC 5.0V 0.5V
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260 C
Note 2: Unused inputs must be held HIGH or LOW. They may not float
DC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
Max
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Max
Min
1.50
0.7 V
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0 5.5 0.7 V
2.0
CC
CC
LOW Level Input
Voltage
0.50
0.50
0.3 V
IL
3.0 5.5
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
V
I
50 A
OH
IN
IH
OH
2.9
4.4
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
I
4 mA
8 mA
OH
OH
OL
V
LOW Level Output
Voltage
0.0
0.0
0.0
0.1
0.1
0.1
0.1
V
IH
50 A
OL
IN
or V
IL
0.1
0.1
0.36
0.36
0.25
0.44
0.44
2.5
I
I
4 mA
8 mA
OL
OL
IL
V
A
I
3-STATE Output
V
V
V
V
V
or V
OZ
IN
IH
V
Off-State Current
or GND
CC
OUT
IN
I
I
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
0.1
4.0
1.0
A
A
5.5V or GND
V or GND
CC
IN
40.0
CC
IN
Noise Characteristics
T
25 C
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum Dynamic
5.0
0.9
1.2
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
L
L
L
L
(Note 3)
V
OL
V
Quiet Output Minimum Dynamic
5.0
5.0
5.0
0.8
1.0
3.5
1.5
V
V
V
OLV
(Note 3)
V
OL
V
Minimum HIGH Level Dynamic
Input Voltage
IHD
(Note 3)
V
Maximum HIGH Level Dynamic
Input Voltage
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
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2
AC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
V
(V)
A
CC
Symbol
Parameter
Units
ns
Conditions
Min
Max
7.0
Min
Max
8.5
t
Propagation Delay
Time
3.3 0.3
5.0
7.5
3.5
5.0
6.8
9.3
4.7
6.2
11.2
6.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
PLH
L
L
L
L
L
L
L
L
L
L
t
10.5
5.0
12.0
6.0
PHL
5.0 0.5
3.3 0.3
5.0 0.5
ns
7.0
8.0
t
3-STATE Output
Enable Time
10.5
14.0
7.2
12.5
16.0
8.5
R
R
1 k
1 k
PZL
L
ns
t
PZH
ns
9.2
10.5
17.5
10.0
t
3-STATE
3.3 0.3
5.0 0.5
15.4
8.8
PLZ
L
t
Output
ns
ns
PHZ
Disable Time
Output to Output Skew
t
3.3 0.3
5.0 0.5
1.5
1.0
10
1.5
1.0
10
(Note 4)
C
C
50 pF
50 pF
OSLH
L
t
OSHL
L
C
Input Capacitance
4
6
pF
pF
V
V
Open
5.0V
IN
CC
CC
C
C
Output Capacitance
OUT
PD
Power Dissipation Capacitance
18
pF (Note 5)
Note 4: Parameter guaranteed by design. t
|t
t
|; t
|t
t
|.
PHLmin
OSLH
PLHmax
PLHmin OSHL
PHLmax
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (OPR.)
C
* V * f
I
/8 (per bit).
CC
PD
CC
IN
CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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