74VHCT08ASJX [FAIRCHILD]
Quad 2-Input AND Gate; 四2输入与门
| 型号： | 74VHCT08ASJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Input AND Gate |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
Revised February 2005
74VHCT08A
Quad 2-Input AND Gate
General Description
Features
The VHCT08A is an advanced high speed CMOS 2 Input
AND Gate fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
■ High speed: tPD 5.0 ns (typ) at TA 25 C
■ High noise immunity: VIH 2.0V, VIL 0.8V
■ Power down protection is provided on all inputs and
outputs
■ Low noise: VOLP 0.8V (max)
■ Low power dissipation:
The internal circuit is composed of 4 stages including buffer
output, which provide high noise immunity and stable out-
put.
ICC
2 A (max) @ TA 25 C
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
■ Pin and function compatible with 74HCT08
the output pins with VCC
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Ordering Code:
Package
Order Number
Package Description
Number
74VHCT08AM
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHCT08AMX_NL
(Note 1)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHCT08ASJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT08AMTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT08AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1)
Wide
74VHCT08AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS500025
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Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
A
L
B
L
O
L
An, Bn
On
L
H
L
L
H
H
L
H
H
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 7.0V
0.5V to 7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to 5.5V
DC Output Voltage (VOUT
(Note 3)
)
Input Voltage (VIN
)
0.5V to VCC 0.5V
0.5V to 7.0V
20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 3)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
Output Diode Current (IOK) (Note 5)
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
(Note 4)
20 mA
Operating Temperature (TOPR
)
40 C to 85 C
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 5.0V 0.5V
)
50 mA
0 ns/V 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
260 C
Note 3: HIGH or LOW state.
I
absolute maximum rating must be
OUT
observed.
Note 4: V
0V.
GND, V
CC
Note 5: V
V
(Outputs Active).
OUT
OUT
CC
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
25 C
Typ
T
40 C to 85 C
Min Max
V
(V)
A
A
CC
Symbol
Parameter
Units
Conditions
Min
2.0
2.0
Max
V
V
V
V
HIGH Level
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
2.0
2.0
IH
V
V
Input Voltage
LOW Level
0.8
0.8
0.8
0.8
IL
Input Voltage
HIGH Level
4.40
3.94
4.50
0.0
4.40
3.80
V
V
V
V
A
A
V
V
V
I
I
I
I
50
A
OH
OL
IN
IN
IH
OH
OH
OL
OL
or V
IL
Output Voltage
LOW Level Output Voltage
8 mA
0.1
0.36
0.1
0.1
0.44
1.0
V
50
A
IH
or V
IL
8 mA
I
Input Leakage Current
0
5.5
V
V
V
5.5V or GND
V or GND
CC
IN
IN
IN
I
Quiescent Supply Current
5.5
5.5
0.0
2.0
20.0
CC
I
Maximum I / Input
CC
3.4V
CCT
IN
1.35
0.5
1.50
5.0
mA
A
Other Inputs
V 5.5V
OUT
V
or GND
CC
I
Output Leakage Current
(Power Down State)
OFF
Noise Characteristics
T
25 C
V
(V)
A
CC
Symbol
Parameter
Quiet Output Maximum Dynamic V
Units
Conditions
Typ
Limit
V
5.0
0.4
0.8
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
(Note 7)
OL
L
L
L
L
V
Quiet Output Minimum Dynamic V
5.0
5.0
5.0
0.4
0.8
2.0
0.8
V
V
V
OLV
(Note 7)
OL
V
Minimum HIGH Level Dynamic Input Voltage
IHD
(Note 7)
V
Maximum LOW Level Dynamic Input Voltage
ILD
(Note 7)
Note 7: Parameter guaranteed by design.
3
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AC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
V
(V)
A
CC
Symbol
Parameter
Propagation Delay
Units
Conditions
Min
Max
6.9
7.9
10
Min
Max
8.0
9.0
10
t
t
5.0
0.5
5.0
5.5
4
1.0
1.0
C
C
15 pF
50 pF
Open
PLH
PHL
L
ns
L
C
C
Input Capacitance
pF
pF
V
CC
IN
Power Dissipation Capacitance
18
(Note 8)
PD
Note 8: C is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained from the equation: I (opr.)
CC
C
* V * f
I
/4 (per gate)
CC
PD
CC
IN
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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