74VHCT245A [FAIRCHILD]
Octal Buffer/Line Driver with 3-STATE Outputs; 八路缓冲器/ 3态输出线路驱动器
| 型号： | 74VHCT245A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1997
Revised April 2005
74VHCT245A
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The VHCT245A is an advanced high speed CMOS octal
bus transceiver fabricated with silicon gate CMOS technol-
ogy. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHCT245A is intended for bidirec-
tional asynchronous communication between data busses.
The direction of data transmission is determined by the
level of the T/R input. The enable input can be used to dis-
able the device so that the busses are effectively isolated.
■ High Speed: tPD 5.4 ns (typ) at VCC 5V
■ Power Down Protection on Inputs and Outputs
■ Low Power Dissipation: ICC
4 A (Max) @ TA 25 C
■ Pin and Function Compatible with 74HCT245
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. These circuits prevent device destruction
due to mismatched supply and input/output voltages. This
device can be used to interface 5V to 3V systems and two
supply systems such as battery back up.
Note 1: Outputs in OFF-State
Ordering Code:
Order Number
74VHCT245AM
74VHCT245ASJ
74VHCT245AMTC
74VHCT245AN
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
M20D
MTC20
N20A
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2005 Fairchild Semiconductor Corporation
DS500004
www.fairchildsemi.com
Pin Descriptions
Pin Names
Description
Output Enable Input
OE
T/R
Transmit/Receive Input
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Truth Table
Inputs
Outputs
T/R
OE
L
L
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
H
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 7.0V
0.5V to 7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
Input Voltage (VIN
)
4.5V to 5.5V
0V to 5.5V
DC Output Voltage (VOUT
(Note 3)
)
)
0.5V to VCC 0.5V
0.5V to 7.0V
20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 3)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
Output Diode Current (IOK) (Note 5)
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
(Note 4)
20 mA
Operating Temperature (TOPR
)
40 C to 85 C
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 5.0V 0.5V
)
75 mA
0 ns/V 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
260 C
Note 3: HIGH or LOW state.
I
absolute maximum rating must be
OUT
observed.
Note 4: When outputs are in OFF-State or when V
OV.
CC
Note 5: V
GND, V
V
(Outputs Active).
OUT
OUT
CC
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
25 C
Typ
T
40 C to 85 C
Min Max
CC
A
A
Symbol
Parameter
Units
Conditions
(V)
Min
2.0
2.0
Max
V
V
V
V
HIGH Level
4.5
5.5
4.5
5.5
2.0
2.0
IH
V
V
Input Voltage
LOW Level
0.8
0.8
0.8
0.8
IL
Input Voltage
HIGH Level
4.40
3.94
4.50
0.0
4.40
3.80
V
V
V
V
A
V
V
V I
IH OH
50
A
OH
OL
IN
4.5
Output Voltage
LOW Level
or V
I
8 mA
IL OH
0.1
0.1
0.44
2.5
V
I
50 A
IN
IH OL
4.5
5.5
Output Voltage
3-STATE Output
Off-State Current
Input Leakage
Current
0.36
0.25
or V
I
8 mA
IL OL
I
I
I
I
I
V
V
V
V
or V
IL
OZ
IN
IH
V or GND
CC
OUT
IN
0–5.5
5.5
0.1
4.0
1.0
40.0
1.50
5.0
A
A
5.5V or GND
IN
Quiescent Supply
Current
V
V
or GND
CC
IN
IN
CC
Maximum I /Input
CC
5.5
1.35
0.5
mA
A
V
3.4V
CCT
OFF
Other Input
5.5V
V
or GND
CC
Output Leakage Current
(Power Down State)
0.0
V
OUT
3
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Noise Characteristics
V
T
25 C
Limits
CC
A
Symbol
Parameter
Units
Conditions
(V)
Typ
V
Quiet Output Maximum Dynamic V
5.0
1.2
1.6
1.6
2.0
0.8
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
OL
L
L
L
L
(Note 7)
V
Quiet Output Minimum Dynamic V
5.0
5.0
5.0
1.2
V
V
V
OLV
OL
(Note 7)
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
IHD
(Note 7)
V
ILD
(Note 7)
Note 7: Parameter guaranteed by design.
AC Electrical Characteristics
V
T
25 C
Typ
T
40 C to 85 C
CC
A
A
Symbol
Parameter
Units
Conditions
(V)
Min
Max
7.7
Min
Max
8.5
t
t
t
t
t
t
t
t
Propagation Delay
Time
4.9
5.4
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
50 pF
PLH
L
L
L
L
L
5.0 0.5
ns
8.7
9.5
PHL
3-STATE Output
Enable Time
3-STATE Output
Disable Time
Output to
9.4
13.8
14.8
15.4
15.0
16.0
16.5
R
R
1 k
1 k
PZL
L
5.0 0.5
5.0 0.5
ns
ns
9.9
PZH
PLZ
10.1
L
PHZ
OSLH
OSHL
5.0 0.5
1.0
10
1.0
10
ns
pF
pF
pF
(Note 8)
Output Skew
Input
C
C
C
4
V
V
Open
5.0V
IN
CC
CC
Capacitance
Output
13
16
OUT
PD
Capacitance
Power Dissipation
Capacitance
(Note 9)
Note 8: Parameter guaranteed by design. t
|t
t
|; t
|t
t
|
OSLH
PLH max
PLH min OSHL
PHL max
PHL min
Note 9: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.)
C
* V * f
I
/8 (per F/F). The total C when n pcs. of the Octal D Flip-Flop operates
CC
PD
CC
IN
CC PD
can be calculated by the equation: C (total) 20 12n.
PD
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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