74VHCT245N [FAIRCHILD]

Bus Transceiver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, PLASTIC, DIP-20;
74VHCT245N
型号: 74VHCT245N
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Bus Transceiver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, PLASTIC, DIP-20

光电二极管 逻辑集成电路
文件: 总10页 (文件大小:149K)
中文:  中文翻译
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March 1998  
74VHC245 74VHCT245  
Octal Bidirectional Transceiver with 3-STATE Outputs  
General Description  
Features  
n High Speed:  
The VHC/VHCT245 is an advanced high speed CMOS octal  
bus transceiver fabricated with silicon gate CMOS technol-  
ogy. It achieves high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation. The VHC245 is intended for bidirectional asyn-  
chronous communication between data busses. The direc-  
tion of data transmission is determined by the level of the  
T/R input. The enable input can be used to disable the de-  
vice so that the busses are effectively isolated. All inputs are  
equipped with protection circuits against static discharge.  
=
=
=
=
VHC tpd 4.0 ns (typ) at VCC 5V  
VHCT tpd 5.3 ns (typ) at VCC 5V  
n High Noise Immunity:  
=
=
VHC VNIH VNIL 28% VCC (Min)  
=
=
VHCT VIH 2.0V, VIL 0.8V  
n Power Down Protection:  
VHC Inputs Only  
VHCT Inputs and Outputs  
n Low Noise:  
=
VHC VOLP 0.9V (typ)  
=
VHCT VOLP 1.1V (typ)  
n Low Power Dissipation:  
=
=
@
ICC 4 µA (Max) TA 25˚C  
n Pin and Function Compatible with 74HC/HCT245  
Ordering Code:  
Commercial  
74VHC245M  
Package Number  
M20B  
Package Description  
20 Lead Molded JEDEC SOIC  
20 Lead Molded EIAJ SOIC  
20 Lead Molded JEDEC Type 1 TSSOP  
20 Lead Molded DIP  
74VHC245SJ  
74VHC245MTC  
74VHC245N  
M20D  
MTC20  
N20A  
74VHCT245M  
74VHCT245SJ  
74VHCT245MTC  
74VHCT245N  
M20B  
20 Lead Molded JEDEC SOIC  
20 Lead Molded EIAJ SOIC  
20 Lead Molded JEDEC Type 1 TSSOP  
20 Lead Molded DIP  
M20D  
MTC20  
N20A  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Assignment for DIP,  
TSSOP and SOIC  
DS011520-2  
DS011520-3  
© 1998 Fairchild Semiconductor Corporation  
DS011520  
www.fairchildsemi.com  
Pin Description  
Truth Tables  
Pin  
Description  
Names  
OE  
Output Enable Input  
T/R  
Transmit/Receive Input  
A0–A7  
B0–B7  
Side A Inputs or 3-STATE Outputs  
Side B Inputs or 3-STATE Outputs  
Inputs  
Outputs  
OE  
T/R  
L
L
L
Bus B Data to Bus A  
Bus A Data to Bus B  
HIGH-Z State  
H
H
X
=
=
=
Immaterial  
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Any unused bus terminals during HIGH-Z State must be held HIGH or LOW.  
www.fairchildsemi.com  
2
Absolute Maximum Ratings (Note 2)  
Recommended Operating  
Conditions (Note 3)  
Supply Voltage (VCC  
)
−0.5V to +7.0V  
−0.5V to 7.0V  
DC Input Voltage (VIN) (T/R , OE )  
Supply Voltage (VCC  
)
DC Output Voltage (VOUT  
VHC  
)
VHC  
2.0V to 5.5V  
4.5V to 5.5V  
0V to 5.5V  
−0.5V to VCC + 0.5V  
−0.5V to 7.0V  
−20 mA  
VHCT (Note 1)  
VHCT (Note 1)  
Input Voltage (VIN)(T/R, OE )  
Output Voltage (VOUT  
Operating Temperature (TOPR  
Input Rise and Fall Time (tr, tf)  
Input Diode Current (IIK) (T/R , OE )  
)
0V to VCC  
Output Diode Current (IOK  
)
)
−40˚C to +85˚C  
±
VHC  
20 mA  
VHCT  
−20 mA  
=
±
±
z
100 ns/V  
VCC 3.3V 0.3V (VHC only)  
0
±
±
DC Output Current (IOUT  
)
25 mA  
75 mA  
=
z
20 ns/V  
VCC 5.0V 0.5V  
0
DC VCC/GND Current (ICC  
)
>
Note 1:  
V
OUT  
V
CC  
only if output is in H or Z state.  
Storage Temperature (TSTG  
Lead Temperature (TL)  
(Soldering, 10 seconds)  
)
−65˚C to +150˚C  
Note 2: Absolute Maximum Ratings are values beyond which the device  
may be damaged or have its useful life impaired. The databook specifications  
should be met, without exception, to ensure that the system design is reliable  
over its power supply, temperature, and output/input loading variables. Fair-  
child does not recommend operation outside databook specifications.  
260˚C  
Note 3: Unused inputs or I/O pins must be held HIGH or LOW. They may not  
float.  
DC Characteristics for VHC Family Devices  
=
=
Symbol  
Parameter  
VCC  
TA 25˚C  
TA −40˚C  
Units  
Conditions  
(V)  
to +85˚C  
Min  
1.50  
Typ  
Max  
Min  
Max  
VIH  
VIL  
High Level Input  
Voltage  
2.0  
3.0–5.5  
2.0  
1.50  
V
V
0.7 VCC  
0.7 VCC  
Low Level Input  
Voltage  
0.50  
0.50  
3.0–5.5  
2.0  
0.3 VCC  
0.3 VCC  
=
=
IOH −50 µA  
VOH  
VOL  
IOZ  
High Level Output  
Voltage  
1.9  
2.9  
2.0  
3.0  
4.5  
1.9  
2.9  
VIN VIH  
3.0  
V
V
or VIL  
4.5  
4.4  
4.4  
=
IOH −4 mA  
3.0  
2.58  
3.94  
2.48  
3.80  
=
IOH −8 mA  
4.5  
=
=
IOL 50 µA  
Low Level Output  
Voltage  
2.0  
0.0  
0.0  
0.0  
0.1  
0.1  
0.1  
0.1  
VIN VIH  
3.0  
V
V
or VIL  
4.5  
0.1  
0.1  
=
IOL 4 mA  
3.0  
0.36  
0.36  
0.44  
0.44  
=
IOL 8 mA  
4.5  
=
3-STATE Output  
Off-State Current  
VIN VCC or GND  
=
±
±
±
5.5  
0–5.5  
5.5  
0.25  
2.5  
1.0  
µA  
µA  
µA  
VOUT VCC or GND  
=
VIN OE VIH or VIL  
=
±
IIN  
Input Leakage  
Current  
0.1  
VIN 5.5V or GND  
(T/R, OE )  
ICC  
=
VIN VCC or GND  
Quiescent Supply  
Current  
4.0  
40.0  
3
www.fairchildsemi.com  
DC Characteristics for VHC Family Devices  
=
Symbol  
Parameter  
VCC  
(V)  
TA 25˚C  
Units  
Conditions  
Typ  
Limits  
=
CL 50 pF  
VOLP (Note 4)  
VOLV (Note 4)  
VIHD (Note 4)  
VILD (Note 4)  
Quiet Output Maximum  
Dynamic VOL  
5.0  
5.0  
5.0  
5.0  
0.9  
1.2  
V
V
V
V
=
CL 50 pF  
Quiet Output Minimum  
Dynamic VOL  
−0.9  
−1.2  
3.5  
=
CL 50 pF  
Minimum High Level  
Dynamic Input Voltage  
Maximum Low Level  
Dynamic Input Voltage  
=
CL 50 pF  
1.5  
Note 4: Parameter guaranteed by design.  
DC Characteristics for VHCT Family Devices  
=
=
Symbol  
Parameter  
VCC  
TA 25˚C  
TA −40˚C  
Units  
Conditions  
(V)  
to +85˚C  
Min  
2.0  
2.0  
Typ  
Max  
Min  
Max  
VIH  
VIL  
High Level  
4.5  
5.5  
4.5  
5.5  
4.5  
4.5  
4.5  
4.5  
2.0  
2.0  
V
V
Input Voltage  
Low Level  
0.8  
0.8  
0.8  
0.8  
Input Voltage  
High Level  
=
=
IOH −50 µA  
VOH  
VOL  
IOZ  
3.15  
2.5  
3.65  
0.0  
3.15  
2.4  
V
V
V
V
VIN VIH  
=
IOH −8 mA  
Output Voltage  
Low Level  
or VIL  
=
=
IOL 50 µA  
0.1  
0.1  
VIN VIH  
=
IOL 8 mA  
Output Voltage  
3-STATE Output  
Off-State Current  
0.36  
0.44  
or VIL  
=
VIN VCC or GND  
=
±
±
±
5.5  
0–5.5  
5.5  
0.25  
2.5  
1.0  
µA  
µA  
µA  
VOUT VCC or GND  
=
VIN OE VIH or VIL  
=
±
IIN  
Input Leakage  
Current  
0.1  
VIN 5.5V or GND  
(T/R, OE )  
ICC  
=
VIN VCC or GND  
Quiescent Supply  
Current  
4.0  
40.0  
1.50  
+5.0  
=
VIN 3.4V  
ICCT  
Maximum ICC/Input  
=
5.5  
0.0  
1.35  
+0.5  
mA  
µA  
Other Inputs VCC  
or GND  
IOFF  
Output Leakage  
Current (Power  
Down State)  
=
VOUT 5.5V  
www.fairchildsemi.com  
4
DC Characteristics for VHCT Family Devices  
=
Symbol  
Parameter  
VCC  
(V)  
TA 25˚C  
Units  
Conditions  
Typ  
Limits  
=
CL 50 pF  
VOLP (Note 5)  
VOLV (Note 5)  
VIHD (Note 5)  
VILD (Note 5)  
Quiet Output Maximum  
Dynamic VOL  
1.1  
1.6  
V
V
V
V
=
CL 50 pF  
Quiet Output Minimum  
Dynamic VOL  
−1.1  
−1.6  
2.0  
=
CL 50 pF  
Minimum High Level  
Dynamic Input Voltage  
Maximum Low Level  
Dynamic Input Voltage  
=
CL 50 pF  
0.8  
Note 5: Parameter guaranteed by design.  
AC Electrical Characteristics for VHC Family Devices  
=
=
Symbol  
Parameter  
VCC  
(V)  
TA 25˚C  
TA −40˚C  
Units  
Conditions  
to +85˚C  
Min  
Typ  
5.8  
Max  
8.4  
Min  
Max  
10.0  
13.5  
6.5  
=
CL 15 pF  
±
tPLH  
Propagation Delay  
Time  
3.3 0.3  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
=
tPHL  
8.3  
11.9  
5.5  
CL 50 pF  
=
±
5.0 0.5  
4.0  
CL 15 pF  
=
5.5  
7.5  
8.5  
CL 50 pF  
=
=
±
tPZL  
tPZH  
3-STATE Output  
Enable Time  
3.3 0.3  
8.5  
13.2  
16.7  
8.5  
15.5  
19.0  
10.0  
12.0  
18.0  
11.0  
1.5  
RL 1 k  
CL 15 pF  
=
11.0  
5.8  
CL 50 pF  
=
±
5.0 0.5  
CL 15 pF  
=
7.3  
10.6  
15.8  
9.7  
CL 50 pF  
=
=
±
tPLZ  
3-STATE Output  
Disable Time  
Output to Output  
Skew  
3.3 0.3  
11.5  
7.0  
RL 1 kΩ  
CL 50 pF  
=
±
tPHZ  
5.0 0.5  
CL 50 pF  
=
±
tOSLH  
tOSHL  
CIN  
3.3 0.3  
1.5  
(Note 6)  
CL 50 pF  
=
±
5.0 0.5  
1.0  
1.0  
CL 50 pF  
=
VCC Open  
Input Capacitance  
4
10  
10  
(T/R, OE )  
CI/O  
=
Output Capacitance  
8
pF  
pF  
VCC 5.0V  
CPD  
Power Dissipation  
Capacitance  
21  
(Note 7)  
=
=
|t  
PHL max  
Note 6: Parameter guaranteed by design. t  
|t  
PLH max  
− t  
|; t  
PLH min OSHL  
− t  
|
PHL min  
OSLH  
Note 7:  
C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average oper-  
PD  
=
*
*
f
IN  
ating current can be obtained by the equation: I  
(opr.)  
C
V
+ I /8 (per Bit).  
CC  
CC  
PD  
CC  
5
www.fairchildsemi.com  
AC Electrical Characteristics for VHCT Family Devices  
=
=
Symbol  
Parameter  
VCC  
(V)  
TA 25˚C  
TA −40˚C  
Units  
Conditions  
to +85˚C  
Min  
Typ  
4.5  
Max  
7.7  
Min  
Max  
8.5  
=
±
tPLH  
tPHL  
tPZL  
tPZH  
tPLZ  
tPHZ  
tOSLH  
tOSHL  
CIN  
Propagation Delay  
Time  
5.0 0.5  
1.0  
1.0  
1.0  
1.0  
1.0  
ns  
ns  
ns  
ns  
CL 15 pF  
=
5.3  
8.7  
9.5  
CL 50 pF  
=
=
±
3-STATE Output  
Enable Time  
5.0 0.5  
8.9  
13.8  
14.8  
15.4  
15.0  
16.0  
16.5  
RL 1 kΩ  
CL 15 pF  
=
9.7  
CL 50 pF  
=
=
±
3-STATE Output  
Disable Time  
5.0 0.5  
10.0  
RL 1 kΩ  
CL 50 pF  
=
±
Output to Output Skew  
5.0 0.5  
1.0  
10  
1.0  
10  
(Note 8)  
CL 50 pF  
=
VCC Open  
Input Capacitance  
Output Capacitance  
4
9
pF  
pF  
=
CI/O  
CPD  
VCC 5.0V  
Power Dissipation  
Capacitance  
(Note 9)  
23  
pF  
=
=
|t  
PHL max  
Note 8: Parameter guaranteed by design. t  
OSLH  
|t  
PLH max  
− t  
|; t  
PLH min OSHL  
− t  
|
PHL min  
Note 9:  
C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average oper-  
PD  
=
*
*
f
IN  
ating current can be obtained by the equation: I  
(opr.)  
C
V
CC  
+ I /8 (per Bit).  
CC  
CC  
PD  
www.fairchildsemi.com  
6
7
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Package —JEDEC SOIC (M)  
Package Number M20B  
20-Lead Small Outline Package EIAJ SOIC (SJ)  
Package Number M20D  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic JEDEC TSSOP Type I (MTC)  
Package Number MTC20  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead (0.300" Wide) Molded Dual-In-Line Package  
Package Number N20A  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-  
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-  
CONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or sys-  
tems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, and (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
Fairchild Semiconductor  
Corporation  
Fairchild Semiconductor  
Europe  
Fairchild Semiconductor  
Hong Kong Ltd.  
National Semiconductor  
Japan Ltd.  
Americas  
Customer Response Center  
Tel: 1-888-522-5372  
Fax: +49 (0) 1 80-530 85 86  
Email: europe.support@nsc.com  
Deutsch Tel: +49 (0) 8 141-35-0  
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Tel: +39 (0) 2 57 5631  
Tel: +852 2737-7200  
Fax: +852 2314-0061  
www.fairchildsemi.com  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  

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