74VHCT374SJX [FAIRCHILD]
Bus Driver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20;
| 型号： | 74VHCT374SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1998
74VHC374 • 74VHCT374
Octal D Flip-Flop with 3-STATE Outputs
General Description
Features
n High Speed:
The VHC/VHCT374 is an advanced high speed CMOS octal
flip-flop with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation. This 8-bit D-type flip-flop is
controlled by a clock input (CP) and an output enable input
(OE ). When the OE input is high, the eight outputs are in a
high impedance state.
=
=
=
VHC tpd 5.4 ns (typ) at VCC 5V
=
VHCT tpd 6.4 ns (typ) at VCC 5V
n High noise immunity:
VHC VNIH VNIL 28% VCC (Min)
=
=
=
=
VHCT VIH 2.0V, VIL 0.8V
n Power down protection:
VHC inputs only
VHCT inputs and outputs
An input protection circuit ensures that 0V–7V can be ap-
plied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and
two supply systems such as battery back up. This circuit pre-
vents device destruction due to mismatched supply and in-
put voltages.
n Low power dissipation:
=
=
@
ICC 4 µA (Max) TA 25˚C
n Pin and function compatible with 74HC/HCT374
Ordering Code:
Commercial
74VHC374M
Package Number
M20B
Package Description
20-Lead Molded JEDEC SOIC
20-Lead Molded EIAJ SOIC
20-Lead Molded JEDEC Type 1 TSSOP
20-Lead Molded DIP
74VHC374SJ
74VHC374MTC
74VHC374N
M20D
MTC20
N20A
74VHCT374M
74VHCT374SJ
74VHCT374MTC
74VHCT374N
M20B
20-Lead Molded JEDEC SOIC
20-Lead Molded EIAJ SOIC
20-Lead Molded JEDEC Type 1 TSSOP
20-Lead Molded DIP
M20D
MTC20
N20A
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Assignment for
DIP, TSSOP and SOIC
DS011538-1
DS011538-2
© 1998 Fairchild Semiconductor Corporation
DS011538
www.fairchildsemi.com
Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
D0–D7
CP
Data Inputs
Dn
H
L
CP
N
N
OE
On
H
L
Clock Pulse Input
3-STATE Output
Enable Input
L
OE
L
H
X
X
Z
O0–O7
3-STATE Outputs
=
=
=
Z
H
L
HIGH Voltage Level
LOW Voltage Level
X
Immaterial
=
High Impedance
N =
LOW-to-HIGH Transition
Functional Description
The VHC/VHCT374 consists of eight edge-triggered
flip-flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE ) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation
of the OE input does not affect the state of the flip-flops.
Logic Diagram
DS011538-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 2)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
DC Output Voltage (VOUT
VHC
)
VHC
2.0V to +5.5V
4.5V to +5.5V
0V to +5.5V
−0.5V to VCC + 0.5V
−0.5V to +7.0V
−20 mA
VHCT
VHCT (Note 1)
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
Input Diode Current (IIK
)
)
0V to VCC
±
Output Diode Current (VHC)
(VHCT)
20 mA
−20 mA
)
−40˚C to +85˚C
±
±
DC Output Current (IOUT
)
25 mA
75 mA
=
±
±
VCC 3.3V 0.3V (VHC only)
0 ns/V – 100 ns/V
0 ns/V – 20 ns/V
DC VCC/GND Current (ICC
)
=
VCC 5.0V 0.5V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65˚C to +150˚C
>
Note 1:
V
OUT
V
CC
only if output is in H or Z state.
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifications
should be met, without exception, to ensure that the system design is reliable
over its power supply, temperature, and output/input loading variables. Fair-
child does not recommend operation outside databook specifications.
260˚C
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics for VHC
=
=
Symbol
Parameter
VCC
TA 25˚C
TA
Units
Conditions
(V)
−40˚C to +85˚C
Min
1.50
Typ
Max
Min
1.50
Max
VIH
VIL
High Level Input
2.0
3.0–5.5
2.0
V
V
Voltage
0.7 VCC
0.7 VCC
Low Level Input Voltage
0.50
0.50
3.0–5.5
2.0
0.3 VCC
0.3 VCC
=
=
IOH −50 µA
VOH
High Level Output
Voltage
1.9
2.9
2.0
3.0
4.5
1.9
2.9
VIN VIH
3.0
V
V
or VIL
4.5
4.4
4.4
=
IOH −4 mA
3.0
2.58
3.94
2.48
3.80
=
IOH −8 mA
4.5
=
=
IOL 50 µA
VOL
Low Level Output
Voltage
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
VIN VIH
3.0
V
V
or VIL
4.5
0.1
0.1
=
IOL 4 mA
3.0
0.36
0.36
0.44
0.44
=
4.5
IOL 8 mA
=
±
±
IOZ
3-STATE Output Off-State
Current
5.5
0.25
2.5
µA
VIN VIH or VIL
=
VOUT VCC or GND
=
±
±
IIN
Input Leakage Current
0–5.5
5.5
0.1
1.0
µA
µA
VIN 5.5V or GND
=
VIN VCC or GND
ICC
Quiescent Supply Current
4.0
40.0
3
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Noise Characteristics for VHC
=
Symbol
Parameter
VCC
(V)
TA 25˚C
Units
Conditions
Typ
Limits
=
CL 50 pF
VOLP
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
5.0
5.0
5.0
5.0
0.6
0.9
−0.9
3.5
V
V
V
V
(Note 4)
=
CL 50 pF
VOLV
(Note 4)
−0.6
=
CL 50 pF
VIHD
(Note 4)
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
=
CL 50 pF
VILD
(Note 4)
1.5
Note 4: Parameter guaranteed by design.
DC Electrical Characteristics for VHCT
=
=
Symbol
Parameter
VCC
TA 25˚C
TA −40˚C
Units
Conditions
(V)
to +85˚C
Min Typ
Max
Min
Max
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
4.5
5.5
4.5
5.5
4.5
2.0
2.0
2.0
2.0
V
V
VIL
0.8
0.8
0.8
0.8
=
=
IOH −50 µA
VOH
VOL
IOZ
3.15 3.65
2.5
3.15
2.4
V
V
VIN VIH
=
or VIL IOH −8 mA
=
=
IOL −50 µA
4.5
5.5
0.0
0.1
0.1
V
VIN VIH
or VIL IOL −8 mA
VIN VIH or VIL
=
0.36
0.44
V
=
±
±
3-STATE Output Off-State
Current
0.25
2.5
µA
=
VOUT VCC or GND
=
±
±
IIN
Input Leakage Current
Quiescent Supply Current
Maximum ICC/Input
0–5.5
5.5
0.1
4.0
1.35
1.0
µA
µA
VIN 5.5V or GND
=
VIN VCC or GND
ICC
ICCT
40.0
1.50
=
VIN 3.4V
5.5
mA
=
Other Inputs VCC or GND
=
±
IOFF
Output Leakage Current
(Power Down State)
0.0
0.5
+5.0
µA
VOUT 5.5V
Noise Characteristics for VHCT
=
Symbol
Parameter
VCC
(V)
TA 25˚C
Units
Conditions
Typ
Limits
1.2
=
CL 50 pF
VOLP (Note 5)
VOLV (Note 5)
VIHD (Note 5)
VILD (Note 5)
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
5.0
5.0
5.0
5.0
0.8
V
V
V
V
=
CL 50 pF
−0.8
−1.2
2.0
=
CL 50 pF
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
=
CL 50 pF
0.8
Note 5: Parameter guaranteed by design.
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4
AC Electrical Characteristics for VHC
=
=
Symbol
Parameter
VCC
(V)
TA 25˚C
TA −40˚C
Units
Conditions
to +85˚C
Min
Typ
8.1
Max
12.7
16.2
8.1
Min
Max
15.0
18.5
9.5
=
CL 15 pF
±
tPLH
tPHL
Propagation Delay Time
(CP to On)
3.3 0.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
=
10.6
5.4
CL 50 pF
=
±
5.0 0.5
CL 15 pF
=
6.9
10.1
11.0
14.5
7.6
11.5
13.0
16.5
9.0
CL 50 pF
=
=
±
tPZL
tPZH
3-STATE Output Enable
Time
3.3 0.3
7.1
ns
RL 1 kΩ
CL 15 pF
=
9.6
CL 50 pF
=
±
5.0 0.5
5.1
ns
CL 15 pF
=
6.6
9.6
11.0
16.0
10.0
1.5
CL 50 pF
=
=
±
tPLZ
3-STATE Output Disable
Time
3.3 0.3
10.2
6.1
14.0
8.8
ns
RL 1 kΩ
CL 50 pF
=
±
tPHZ
tOSLH
tOSHL
fmax
5.0 0.5
CL 50 pF
=
±
Output to Output Skew
3.3 0.3
1.5
ns
(Note 6)
CL 50 pF
=
±
5.0 0.5
1.0
1.0
CL 50 pF
=
±
Maximum Clock Frequency
3.3 0.3
80
55
130
85
185
120
4
70
50
MHz
CL 15 pF
=
CL 50 pF
=
±
5.0 0.5
130
85
110
75
CL 15 pF
=
CL 50 pF
=
VCC Open
CIN
Input Capacitance
Output Capacitance
10
10
pF
pF
pF
=
COUT
CPD
6
VCC 5.0V
Power Dissipation
Capacitance
32
(Note 7)
=
=
|t
PHL max
Note 6: Parameter guaranteed by design. t
|t
PLH max
− t
|; t
PLH min OSHL
− t
|
PHL min
OSLH
Note 7:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average oper-
=
*
*
f
IN
ating current can be obtained by the equation: I
(opr.)
C
PD
V
CC
+ I /8 (per F/F). The total C when n pcs. of the Octal D Flip-Flop operates can be
CC PD
CC
calculated by the equation: C (total) 20 + 12n.
=
PD
AC Operating Requirements for VHC
=
=
Symbol
Parameter
VCC
(V)
TA 25˚C
TA −40˚C
Units
Conditions
to +85˚C
Min
5.0
5.0
4.5
3.0
2.0
2.0
Typ
Max
Min
Max
±
tW(H)
tW(L)
tS
Minimum Pulse Width (CP)
Minimum Set-Up Time
Minimum Hold Time
3.3 0.3
5.5
5.0
4.5
3.0
2.0
2.0
ns
ns
±
5.0 0.5
±
3.3 0.3
±
5.0 0.5
±
3.3 0.3
tH
±
5.0 0.5
5
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AC Electrical Characteristics for VHCT
=
=
Symbol
Parameter
VCC
(V)
TA 25˚C
TA −40˚C
Units
Conditions
to +85˚C
Min
Typ
5.6
6.4
6.5
7.3
7.0
Max
9.4
Min
1.0
1.0
1.0
1.0
1.0
Max
10.5
11.5
11.5
12.5
12.0
=
CL 15 pF
±
tPLH
tPHL
tPZL
Propagation
Delay Time
5.0 0.5
ns
ns
ns
=
10.4
10.2
11.2
11.2
CL 50 pF
=
=
±
3-STATE Output
Enable Time
5.0 0.5
RL 1 kΩ
CL 15 pF
=
tPZH
tPLZ
CL 50 pF
=
=
±
3-STATE Output
Disable Time
5.0 0.5
RL 1 kΩ
CL 50 pF
tPHZ
tOSLH
tOSHL
fmax
±
Output to Output
Skew
5.0 0.5
1.0
1.0
(Note 8)
=
±
Maximum Clock
Frequency
5.0 0.5
90
85
140
130
4
80
75
MHz
pF
CL 15 pF
=
CL 50 pF
=
VCC Open
CIN
Input
10
10
Capacitance
=
COUT
CPD
Output
9
pF
pF
VCC 5.0V
Capacitance
Power Dissipation
Capacitance
27
(Note 9)
=
=
|t
PHL max
Note 8: Parameter guaranteed by design. t
OSLH
|t
PLH max
− t
|; t
PLH min OSHL
− t
|
PHL min
Note 9:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average oper-
=
*
*
f
IN
ating current can be obtained by the equation: I
(opr.)
C
V
CC
+ I /8 (per F/F).
CC
CC
PD
AC Operating Requirements for VHCT
=
=
Symbol
Parameter
VCC
(V)
TA 25˚C
TA −40˚C
Units
to +85˚C
Min
Typ
Max
Min
Max
±
tW(H)
tW(L)
tS
Minimum Pulse
Width (CP)
Minimum Set-up
Time
5.0 0.5
6.5
6.5
2.5
2.5
ns
ns
±
5.0 0.5
2.5
2.5
±
5.0 0.5
tH
Minimum Hold
Time
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6
7
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit—JEDEC SOIC (M)
Package Number M20B
20-Lead Plastic EIAJ SOIC (SJ)
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic JEDEC TSSOP Type 1 (MTC)
Package Number MTC20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.300" Wide) Molded Dual-In-Line Package
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Corporation
Fairchild Semiconductor
Europe
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Hong Kong Ltd.
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