74VHCT540AMX [FAIRCHILD]
8-Bit Inverting Buffer/Driver ; 8位缓冲器/驱动器\n
| 型号： | 74VHCT540AMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Inverting Buffer/Driver
|
| 文件： | 总6页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1997
Revised April 1999
74VHCT540A
Octal Buffer/Line Driver with 3-STATE Outputs
Protection circuits ensure that 0V to 7V can be applied to
General Description
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to mis-
matched supply and input voltages.
The VHCT540A is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
Note 1: Outputs in OFF-STATE
The VHCT540A is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
Features
■ High Speed:
t
PD = 5.4 ns (typ) at VCC = 5V
CC = 4 µA (max) at TA = 25°C
This device is similar in function to the VHCT240A while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
■ Low Power Dissipation:
I
■ Power down protection is provided on all inputs and
outputs
■ Pin and function compatible with 74HCT540
Ordering Code:
Order Number
74VHCT540AM
74VHCT540ASJ
74VHCT540AMTC
74VHCT540AN
Package Number
M20B
Package Dissipation
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
M20D
MTC20
N20A
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
OE1, OE2
I0 - I7
3-STATE Output Enable Inputs
Inputs
OE1
OE2
I
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
O0 - O7
3-STATE Outputs
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
© 1999 Fairchild Semiconductor Corporation
DS500012.prf
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
4.5V to +5.5V
0V to +5.5V
DC Output Voltage (VOUT
(Note 3)
)
Input Voltage (VIN
)
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 4)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
)
(Note 3)
Output Diode Current (IOK
(Note 5)
)
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
CC = 5.0V ± 0.5V
)
−40°C to +85°C
±20 mA
±25 mA
DC Output Current (IOUT
)
V
0 ≈ 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
DC VCC/GND Current (ICC
)
±75 mA
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
260°C
Note 3: When outputs are in OFF-STATE or when V = OV.
CC
Note 4: HIGH or LOW state.
I
absolute maximum rating must be
OUT
observed.
Note 5: V
<GND, V
> V
OUT CC (outputs active).
OUT
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
Max
V
V
V
HIGH Level Input Voltage 4.5 − 5.5
LOW Level Input Voltage 4.5 − 5.5
2.0
2.0
V
V
V
V
V
V
IH
0.8
0.8
IL
HIGH Level
4.5
4.5
4.5
4.5
4.4
4.5
0.0
4.4
V
V
= V
I
OH
= −50 µA
= −8 mA
= 50 µA
= 8 mA
OH
IN
IH
Output Voltage
LOW Level
3.94
3.80
or V
I
IL OH
V
0.1
0.1
= V
I
OL
OL
IN
IH
Output Voltage
0.36
0.44
or V
I
IL OL
I
3-STATE Output
OFF-STATE Current
V
V
= V or V
IH IL
OZ
IN
5.5
±0.25
±2.5
µA
= V or GND
OUT
CC
I
I
I
Input Leakage Current
0 − 5.5
±0.1
±1.0
µA
µA
V
V
V
= 5.5V or GND
IN
IN
IN
IN
Quiescent Supply Current
5.5
4.0
40.0
= V or GND
CC
CCT
CC
Maximum I
= 3.4V
CC/input
5.5
0
1.35
0.5
1.50
5.0
mA
other inputs = V or GND
CC
I
Output Leakage Current
µA
V
= 5.5V
OFF
OUT
Noise Characteristics
T
= 25°C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum
OLP
5.0
1.2
1.6
V
V
V
V
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
(Note 7)
Dynamic V
OL
V
Quiet Output Minimum
Dynamic V
OLV
5.0
5.0
5.0
−1.2
1.6
2.0
0.8
(Note 7)
OL
V
Minimum HIGH Level Dynamic
Input Voltage
IHD
(Note 7)
V
Maximum HIGH Level Dynamic
Input Voltage
ILD
(Note 7)
Note 7: Parameter guaranteed by design.
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2
AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
ns
Conditions
Min
Typ
5.4
5.9
8.3
8.8
Max
7.4
Min
Max
8.5
t
t
t
t
t
t
t
t
Propagation Delay
Time
1.0
1.0
1.0
1.0
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
PLH
L
L
L
L
5.0 ± 0.5
8.4
9.5
PHL
3-STATE Output
Enable Time
11.3
12.3
13.0
14.0
PZL
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
ns
R
R
= 1 kΩ
= 1 kΩ
L
L
PZH
PLZ
3-STATE Output
Disable Time
9.4
11.9
1.0
13.5
ns
C
= 50 pF
= 50 pF
L
L
PHZ
OSLH
OSHL
Output to Output
Skew
1.0
10
1.0
10
ns (Note 8)
C
C
C
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
4
9
pF
pF
V
V
= Open
IN
CC
CC
= 5.0V
OUT
PD
19
pF (Note 9)
Note 8: Parameter guaranteed by design. t
= |t
− t
|; t
= |t
− t
|.
PHLmin
OSLH
PLHmax
PLHmin OSLH
PHLmax
Note 9: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.) = C * V * f + I /8 (per bit).
CC
PD
CC
IN
CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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